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VERILOG CODE
MODULE 3
1. HALF ADDER
A>BM
module ha(sum,carry,a,b);
output sum,carry;
input a,b;
reg sum,carry;
always @(a,b)
begin
 sum=a^b;
 carry=a&b;
end
Endmodule
B>DM
module ha(sum,carry,a,b);
output sum,carry;
input a,b;
assign sum=a^b;
assign carry=a&b;
endmodule
C>SM
module ha(sum,carry,a,b);
output sum,carry;
input a,b;
xor x1(sum,a,b);
and a1(carry,a,b);
Endmodule
2. FULL ADDER
A>BM
module full_adder_behavioral (
 input a, b, cin,
 output sum, cout
);
 output sum;
 output cout;
 input a;
 input b;
 input cin;
 reg sum;
 reg cout;
 // Behavioral logic
 always @* begin
 sum = a ^ b ^ cin;
 cout = (a & b) | (b & cin) | (a & cin);
 end
endmodule
B>DM
module full_adder_dataflow (
 input a, b, cin,
 output sum, cout
);
 output sum;
 output cout;
 input a;
 input b;
 input cin;
 // Dataflow logic
 assign sum = a ^ b ^ cin;
 assign cout = (a & b) | (b & cin) | (a & cin);
endmodule
C>SM using half adder
module full_adder_structural (
 input a, b, cin,
 output sum, cout
);
 output sum;
 output cout;
 input a;
 input b;
 input cin;
 // Internal signals
 wire s1, c1, c2;
 // InstanƟate half adders and OR gate
 half_adder HA1(a, b, s1, c1);
 half_adder HA2(s1, cin, sum, c2);
 assign cout = c1 | c2;
endmodule
// Half Adder Module DefiniƟon
module half_adder (
 input a, b,
 output sum, carry
);
 // Output declaraƟons
 output sum;
 output carry;
 // Input declaraƟons
 input a;
 input b;
 // Dataflow logic
 assign sum = a ^ b;
 assign carry = a & b;
endmodule
3. HALF SUBTRACTOR
A>BM
module half_subtractor_behavioral (
 input a, b,
 output difference, borrow
);
 // Output declaraƟons
 output difference;
 output borrow;
 // Input declaraƟons
 input a;
 input b;
 // Behavioral modeling
 assign difference = a ^ b;
 assign borrow = (~a) & b;
endmodule
B>DM
module half_subtractor_dataflow (
 input a, b,
 output difference, borrow
);
 // Output declaraƟons
 output difference;
 output borrow;
 // Input declaraƟons
 input a;
 input b;
 // Dataflow modeling
 assign difference = a ^ b;
 assign borrow = (~a) & b;
endmodule
C>SM
module half_subtractor_structural (
 input a, b,
 output difference, borrow
);
 // Output declaraƟons
 output difference;
 output borrow;
 // Input declaraƟons
 input a;
 input b;
 // Internal signals
 wire diff_intermediate;
 // Structural modeling
 xor gate_diff(diff_intermediate, a, b);
 and gate_borrow(borrow, ~a, b);
 // Output assignment
 assign difference = diff_intermediate;
endmodule
4. FULL SUBTRACTOR
A>BM
module full_subtractor_behavioral (a, b, bin,
difference, bout);
 input a, b, bin;
 output difference, bout;
 // XOR gate for difference
 assign difference = a ^ b ^ bin;
 // Generate and propagate signals
 wire gen = (~a & b) | (~a & bin) | (b & bin);
 wire prop = ~a | b | bin;
 // Borrow output
 assign bout = gen | prop;
endmodule
B>DM
module full_subtractor_dataflow (a, b, bin,
difference, bout);
 input a, b, bin;
 output difference, bout;
 // Dataflow modeling using assignments
 assign difference = a ^ b ^ bin;
 assign bout = (~a & b) | (~a & bin) | (b & bin);
endmodule
C>SM
module xor_gate (input a, input b, output y);
 assign y = a ^ b;
endmodule
module and_gate (input a, input b, output y);
 assign y = a & b;
endmodule
module not_gate (input a, output y);
 assign y = ~a;
endmodule
module full_subtractor_structural (a, b, bin,
difference, bout);
 input a, b, bin;
 output difference, bout;
 // Internal signals
 wire w1, w2, w3, w4, w5;
 // Components instanƟaƟon
 xor_gate xor1 (a, b, w1);
 xor_gate xor2 (w1, bin, difference);
 and_gate and1 (w1, bin, w2);
 and_gate and2 (a, ~b, w3);
 and_gate and3 (~a, b, w4);
 or_gate or1 (w2, w3, w5);
 or_gate or2 (w5, w4, bout);
endmodule
D>SM using half subtractor
module half_subtractor (
 input a, b,
 output difference, borrow
);
 assign difference = a ^ b;
 assign borrow = (~a & b);
endmodule
module full_subtractor (
 input a, b, bin,
 output difference, bout
);
 wire diff1, bout1;
 half_subtractor hs1 (a, b, diff1, bout1);
 half_subtractor hs2 (diff1, bin, difference, bout);
 assign bout = bout1 | (b & bin);
endmodule
==========================================
MODULE 4
1. DECODER
module decoder3x8 (
 input [2:0] sel,
 output reg [7:0] out
);
always @* begin
 case(sel)
 3'b000: out = 8'b00000001;
 3'b001: out = 8'b00000010;
 3'b010: out = 8'b00000100;
 3'b011: out = 8'b00001000;
 3'b100: out = 8'b00010000;
 3'b101: out = 8'b00100000;
 3'b110: out = 8'b01000000;
 3'b111: out = 8'b10000000;
 default: out = 8'b00000000;
 endcase
end
endmodule
module tb_decoder3x8;
 // Inputs
 reg [2:0] sel;
 // Outputs
 wire [7:0] out;
 // InstanƟate the decoder3x8 module
 decoder3x8 uut (
 .sel(sel),
 .out(out)
 );
 // SƟmulus
 iniƟal begin
 // Apply test cases
 for (int i = 0; i < 8; i++) begin
 // Set inputs
 sel = i;
 // Wait for a few Ɵme units
 #10;
 end
 // End simulaƟon
 $finish;
 end
endmodule
ENCODER
//- 8:3 Encoder:
module encoder8_3(i, en, y);
 input [7:0] i;
 input en;
 output reg [2:0] y;
 always @(i, en) begin
 if (en == 0)
 y = 0;
 else begin
 case(i)
 8'b00000001: y = 3'b000;
 8'b00000010: y = 3'b001;
 8'b00000100: y = 3'b010;
 8'b00001000: y = 3'b011;
 8'b00010000: y = 3'b100;
 8'b00100000: y = 3'b101;
 8'b01000000: y = 3'b110;
 8'b10000000: y = 3'b111;
 endcase
 end
 end
endmodule
module tb_encoder8_3;
 // Inputs
 reg [7:0] i;
 reg en;
 // Outputs
 wire [2:0] y;
 // InstanƟate the encoder8_3 module
 encoder8_3 uut (
 .i(i),
 .en(en),
 .y(y)
 );
 // SƟmulus
 iniƟal begin
 // Define test cases
 int num_test_cases = 9; // One extra test case
for disabling the encoder
 int test_i[num_test_cases] = '{8'b00000001,
8'b00000010, 8'b00000100, 8'b00001000,
 8'b00010000, 8'b00100000,
8'b01000000, 8'b10000000, 8'b00000000};
 // Apply test cases
 for (int i = 0; i < num_test_cases; i++) begin
 // Set inputs
 i = test_i[i];
 en = (i != 8'b00000000); // Enable the encoder
for all test cases except when input is all zeroes
 // Wait for a few Ɵme units
 #10;
 end
 // End simulaƟon
 $finish;
 end
endmodule
PRIORITY ENCODER
module priority_encoder_4to2 (
 input [3:0] D,
 output reg [1:0] x,
 output reg V,
 output reg y
);
always @* begin
 case (D)
 4'b0000: {x, V, y} = 3'b000;
 4'b0001: {x, V, y} = {2'b01, 1'b1, 1'b0};
 4'b0010: {x, V, y} = {2'b10, 1'b1, 1'b0};
 4'b0011: {x, V, y} = {2'b11, 1'b1, 1'b0};
 default: {x, V, y} = {2'b00, 1'b0, 1'b1};
 endcase
end
endmodule
2. MUX
2*1 MUX with TB
module mux_2to1 (
 input a, b, sel,
 output out
);
 assign out = (sel == 1'b0) ? a : b;
endmodule
module tb_mux_2to1;
 // Inputs
 reg a, b, sel;
 // Output
 wire out;
 // InstanƟate the mux_2to1 module
 mux_2to1 uut (
 .a(a),
 .b(b),
 .sel(sel),
 .out(out)
 );
 // SƟmulus
 iniƟal begin
 // Define test cases
 int num_test_cases = 4;
 int test_data[num_test_cases][3] = '{ {1, 0, 0}, {1,
0, 1}, {0, 1, 0}, {0, 1, 1} };
 // Apply test cases
 for (int i = 0; i < num_test_cases; i++) begin
 // Set inputs
 a = test_data[i][0];
 b = test_data[i][1];
 sel = test_data[i][2];
 // Wait for a few Ɵme units
 #10;
 end
 // End simulaƟon
 $finish;
 end
endmodule
4*1 MUX with TB
module mux_4to1 (
 input [3:0] data,
 input [1:0] sel,
 output out
);
 assign out = (sel == 2'b00) ? data[0] :
 (sel == 2'b01) ? data[1] :
 (sel == 2'b10) ? data[2] :
 data[3];
endmodule
module tb_mux_4to1;
 // Inputs
 reg [3:0] data;
 reg [1:0] sel;
 // Output
 wire out;
 // InstanƟate the mux_4to1 module
 mux_4to1 uut (
 .data(data),
 .sel(sel),
 .out(out)
 );
 // SƟmulus
 iniƟal begin
 // Define test cases
 int num_test_cases = 4;
 int test_data[num_test_cases][2] = '{ {2'b00,
4'b0001}, {2'b01, 4'b0010}, {2'b10, 4'b0100},
{2'b11, 4'b1000} };
 // Apply test cases
 for (int i = 0; i < num_test_cases; i++) begin
 // Set inputs
 sel = test_data[i][0];
 data = test_data[i][1];
 // Wait for a few Ɵme units
 #10;
 end
 // End simulaƟon
 $finish;
 end
endmodule
8*1 MUX with TB
module mux_8to1 (
 input [7:0] data,
 input [2:0] sel,
 output out
);
 assign out = (sel == 3'b000) ? data[0] :
 (sel == 3'b001) ? data[1] :
 (sel == 3'b010) ? data[2] :
 (sel == 3'b011) ? data[3] :
 (sel == 3'b100) ? data[4] :
 (sel == 3'b101) ? data[5] :
 (sel == 3'b110) ? data[6] :
 data[7];
endmodule
module tb_mux_8to1;
 // Inputs
 reg [7:0] data;
 reg [2:0] sel;
 // Output
 wire out;
 // InstanƟate the mux_8to1 module
 mux_8to1 uut (
 .data(data),
 .sel(sel),
 .out(out)
 );
 // SƟmulus
 iniƟal begin
 // Define test cases
 int num_test_cases = 8;
 int test_data[num_test_cases][2] = '{ {3'b000,
8'b00000001}, {3'b001, 8'b00000010},
 {3'b010, 8'b00000100},
{3'b011, 8'b00001000},
 {3'b100, 8'b00010000},
{3'b101, 8'b00100000},
 {3'b110, 8'b01000000},
{3'b111, 8'b10000000} };
 // Apply test cases
 for (int i = 0; i < num_test_cases; i++) begin
 // Set inputs
 sel = test_data[i][0];
 data = test_data[i][1];
 // Wait for a few Ɵme units
 #10;
 end
 // End simulaƟon
 $finish;
 end
 Endmodule
3. DEMUX
1*4 DEMUX with TB
module demux_1to4 (
 input data,
 input [1:0] sel,
 output out0, out1, out2, out3
);
 assign out0 = (sel == 2'b00) ? data : 1'b0;
 assign out1 = (sel == 2'b01) ? data : 1'b0;
 assign out2 = (sel == 2'b10) ? data : 1'b0;
 assign out3 = (sel == 2'b11) ? data : 1'b0;
endmodule
module tb_demux_1to4;
 // Inputs
 reg data;
 reg [1:0] sel;
 // Outputs
 wire out0, out1, out2, out3;
 // InstanƟate the demux_1to4 module
 demux_1to4 uut (
 .data(data),
 .sel(sel),
 .out0(out0),
 .out1(out1),
 .out2(out2),
 .out3(out3)
 );
 // SƟmulus
 iniƟal begin
 // Define test cases
 int num_test_cases = 4;
 int test_data[num_test_cases] = '{1'b1, 1'b0,
1'b1, 1'b0};
 int test_sel[num_test_cases][2] = '{ {2'b00},
{2'b01}, {2'b10}, {2'b11} };// Apply test cases
 for (int i = 0; i < num_test_cases; i++) begin
 // Set inputs
 data = test_data[i];
 sel = test_sel[i];
 // Wait for a few Ɵme units
 #10;
 end
 // End simulaƟon
 $finish;
 end
endmodule
1*8 DEMUX with TB
module demux_1to8 (
 input data,
 input [2:0] sel,
 output out0, out1, out2, out3, out4, out5, out6,
out7
);
 assign out0 = (sel == 3'b000) ? data : 1'b0;
 assign out1 = (sel == 3'b001) ? data : 1'b0;
 assign out2 = (sel == 3'b010) ? data : 1'b0;
 assign out3 = (sel == 3'b011) ? data : 1'b0;
 assign out4 = (sel == 3'b100) ? data : 1'b0;
 assign out5 = (sel == 3'b101) ? data : 1'b0;
 assign out6 = (sel == 3'b110) ? data : 1'b0;
 assign out7 = (sel == 3'b111) ? data : 1'b0;
endmodule
module tb_demux_1to8;
 // Inputs
 reg data;
 reg [2:0] sel;
 // Outputs
 wire out0, out1, out2, out3, out4, out5, out6,
out7;
 // InstanƟate the demux_1to8 module
 demux_1to8 uut (
 .data(data),
 .sel(sel),
 .out0(out0),
 .out1(out1),
 .out2(out2),
 .out3(out3),
 .out4(out4),
 .out5(out5),
 .out6(out6),
 .out7(out7)
 );
 // SƟmulus
 iniƟal begin
 // Define test cases
 int num_test_cases = 8;
 int test_data[num_test_cases] = '{1'b1, 1'b0,
1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0};
 int test_sel[num_test_cases][3] = '{ {3'b000},
{3'b001}, {3'b010}, {3'b011},
 {3'b100}, {3'b101}, {3'b110},
{3'b111} };
 // Apply test cases
 for (int i = 0; i < num_test_cases; i++) begin
 // Set inputs
 data = test_data[i];
 sel = test_sel[i];
 // Wait for a few Ɵme units
 #10;
 end
 // End simulaƟon
 $finish;
 end
endmodule
3*8 DEMUX with TB
module demux_3to8 (
 input [2:0] sel,
 input data,
 output out0, out1, out2, out3, out4, out5, out6,
out7
);
 assign out0 = (sel == 3'b000) ? data : 1'b0;
 assign out1 = (sel == 3'b001) ? data : 1'b0;
 assign out2 = (sel == 3'b010) ? data : 1'b0;
 assign out3 = (sel == 3'b011) ? data : 1'b0;
 assign out4 = (sel == 3'b100) ? data : 1'b0;
 assign out5 = (sel == 3'b101) ? data : 1'b0;
 assign out6 = (sel == 3'b110) ? data : 1'b0;
 assign out7 = (sel == 3'b111) ? data : 1'b0;
endmodule
module tb_demux_3to8;
 // Inputs
 reg [2:0] sel;
 reg data;
 // Outputs
 wire out0, out1, out2, out3, out4, out5, out6,
out7;
 // InstanƟate the demux_3to8 module
 demux_3to8 uut (
 .sel(sel),
 .data(data),
 .out0(out0),
 .out1(out1),
 .out2(out2),
 .out3(out3),
 .out4(out4),
 .out5(out5),
 .out6(out6),
 .out7(out7)
 );
 // SƟmulus
 iniƟal begin
 // Define test cases
 int num_test_cases = 8;
 int test_data[num_test_cases] = '{1'b1, 1'b0,
1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0};
 int test_sel[num_test_cases][3] = '{ {3'b000},
{3'b001}, {3'b010}, {3'b011},
 {3'b100}, {3'b101}, {3'b110},
{3'b111} };
 // Apply test cases
 for (int i = 0; i < num_test_cases; i++) begin
 // Set inputs
 data = test_data[i];
 sel = test_sel[i];
 // Wait for a few Ɵme units
 #10;
 end
 // End simulaƟon
 $finish;
 end
endmodule
4. PARITY GEN.
Verilog code for a parity generator and checker for
both even and odd parity, for both 3-bit and 4-bit
inputs:
module parity_gen_chk_3bit (
 input [2:0] data,
 output reg even_parity,
 output reg odd_parity
);
assign even_parity = ^data;
assign odd_parity = ^~data;
endmodule
module parity_gen_chk_4bit (
 input [3:0] data,
 output reg even_parity,
 output reg odd_parity
);
assign even_parity = ^data;
assign odd_parity = ^~data;
endmodule
1. PARALLEL ADDER
(a)
module fadder (A, B, Cin, Sum, Cout);
input A, B, Cin;
output Sum, Cout;
wire t1, t2, t3, t4;
xor x1(t1, A, B);
xor x2(Sum, t1, Cin);
and g1(t2, A, B);
and g2(t3, B, Cin);
and g3(t4, Cin, A);
or g4(Cout, t2, t3, t4);
endmodule
module add_sub_4 (A, B, M, S, C5);
input [3:0] A, B;
input M;
output [3:0] S;
output C5;
wire C2, C3, C4, t5, t6, t7, t8;
xor x3(t5, B[1], M);
xor x4(t6, B[2], M);
xor x5(t7, B[3], M);
xor x6(t8, B[4], M);
fadder f1(A[1], t5, M, S[1], C2);
fadder f2(A[2], t6, C2, S[2], C3);
fadder f3(A[3], t7, C3, S[3], C4);
fadder f4(A[4], t8, C4, S[4], C5);
endmodule
(b) alternative
module full_adder (
 input a,
 input b,
 input cin,
 output sum,
 output cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule
module parallel_adder (
 input [3:0] A,
 input [3:0] B,
 output [3:0] S,
 output C_out
);
wire [3:0] carry;
full_adder fa[3:0](
 .a(A),
 .b(B),
 .cin({C_out, carry[2:0]}),
 .sum(S),
 .cout(carry)
);
assign C_out = carry[3];
endmodule
PARALLEL SUBTRACTOR
module parallel_subtractor (
 input [3:0] A,
 input [3:0] B,
 output [3:0] S,
 output C_out
);
wire [3:0] B_inv;
wire C_in;
// Compute two's complement of B
assign B_inv = ~B + 1;
// Perform addiƟon of A and two's complement of
B
parallel_adder pa (
 .A(A),
 .B(B_inv),
 .S(S),
 .C_out(C_in)
);
// Invert the carry out to get borrow out
assign C_out = ~C_in;
endmodule
6. 4-bit binary adder: one using
module instantiation and the other
using behavioral modeling.
a> Binary Adder using Module
Instantiation:
module main(
 input [3:0] in1,
 input [3:0] in2,
 input ic,
 output [3:0] out,
 output [3:0] oc
);
 fulladder fa1(in1[0], in2[0], ic, out[0], oc[0]);
 fulladder fa2(in1[1], in2[1], oc[0], out[1], oc[1]);
 fulladder fa3(in1[2], in2[2], oc[1], out[2], oc[2]);
 fulladder fa4(in1[3], in2[3], oc[2], out[3], oc[3]);
endmodule
module fulladder(
 input a,
 input b,
 input ic,
 output o,
 output oc
);
 assign o = (~ic & ((a & ~b) | (~a & b))) | (ic & ~((a
& ~b) | (~a & b)));
 assign oc = (a & b) | (b & ic) | (ic & a);
endmodule
b> Binary Adder using Behavioral Modeling:
module 4_bit_Add(
 input [3:0] a, b,
 input Cin,
 output [3:0] sum,
 output Cout
);
 reg [3:0] sum;
 reg Cout;
 always @* begin
 {Cout, sum} = a + b + Cin;
 end
endmodule
7. 4-bit Carry Look-Ahead Adder (CLA)
along with a testbench:
module CLA_Adder(
 input [3:0] a, b,
 input cin,
 output [3:0] sum,
 output cout
);
 wire p0, p1, p2, p3, g0, g1, g2, g3, c1, c2, c3, c4;
 assign p0 = a[0] ^ b[0];
 assign p1 = a[1] ^ b[1];
 assign p2 = a[2] ^ b[2];
 assign p3 = a[3] ^ b[3];
 assign g0 = a[0] & b[0];
 assign g1 = a[1] & b[1];
 assign g2 = a[2] & b[2];
 assign g3 = a[3] & b[3];
 assign c1 = g0 | (p0 & cin);
 assign c2 = g1 | (p1 & g0) | (p1 & p0 & cin);
 assign c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p1
& p1 & p0 & cin);
 assign c4 = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3
& p2 & p1 & g0) | (p3 & p2 & p1 & p0 & cin);
 assign sum[0] = p0 ^ cin;
 assign sum[1] = p1 ^ c1;
 assign sum[2] = p2 ^ c2;
 assign sum[3] = p3 ^ c3;
 assign cout = c4;
endmodule
module TestModule;
 // Inputs
 reg [3:0] a, b;
 reg cin;
 // Outputs
 wire [3:0] sum;
 wire cout;
 // InstanƟate the Unit Under Test (UUT)
 CLA_Adder uut (a, b, cin, sum, cout);
 iniƟal begin
 // IniƟalize Inputs
 a = 0;
 b = 0;
 cin = 0;
 // Wait 100 ns for global reset to finish
 #100;
 // Change inputs
 a = 5;
 b = 7;
 cin = 1;
 // Wait 100 ns for global reset to finish
 #100;
 // Finish simulaƟon
 $finish;
 end
endmodule
8. binary multiplier and its testbench
// Code your design here
module Mul(
 input [3:0] a, b,
 output reg [7:0] mul_res
);
 always @(a or b) begin
 mul_res = a * b;
 end
endmodule
// Testbench
module testbench;
 reg [3:0] a, b;
 wire [7:0] mul_res;
 integer i;
 // InstanƟate the Mul module
 Mul uut (
 .a(a),
 .b(b),
 .mul_res(mul_res)
 );
 // IniƟal block to set iniƟal values of a and b
 iniƟal begin
 a = 0;
 b = 0;
 end
 // SƟmulus generaƟon
 always @(a or b) begin
 for (i = 0; i < 16 * 16; i = i + 1) begin
 {a, b} = i;
 #10;
 end
 $stop;
 end
endmodule
9. 4x4 array multiplier
module MulƟply_4x4(
 input [3:0] a,
 input [3:0] b,
 output [7:0] p
);
 wire [3:0] pp0, pp1, pp2, pp3;
 wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11;
 wire s1, s2, s3, s4, s5, s6;
 assign pp0 = a[0] * b[3:0];
 assign pp1 = a[1] * b[3:0];
 assign pp2 = a[2] * b[3:0];
 assign pp3 = a[3] * b[3:0];
 assign p[0] = pp0[0];
 assign p[1] = pp0[1];
 assign p[2] = pp0[2];
 assign p[3] = pp0[3];
 assign p[4] = pp1[3:0] + pp2[2:0] + pp3[1:0];
 assign p[5] = pp2[3:1] + pp3[2:0];
 assign p[6] = pp3[3] + c10;
 assign p[7] = c11;
 // Half adder module
 halfadder HA1(pp0[1], pp1[0], p[1], c1);
 halfadder HA2(pp2[0], pp1[1], p[2], c3);
 halfadder HA3(pp3[0], pp2[1], p[3], c6);
 halfadder HA4(pp3[1], pp2[2], p[4], c9);
 // Full adder module
 fulladder FA1(pp0[2], pp1[1], pp1[2], s1, c2);
 fulladder FA2(s1, pp0[3], pp1[2], s2, c4);
 fulladder FA3(s2, pp1[2], pp2[1], s3, c5);
 fulladder FA4(s2, pp1[3], pp2[2], s4, c7);
 fulladder FA5(s4, pp2[3], pp3[2], s5, c8);
 fulladder FA6(s5, pp2[3], pp3[2], s6, c10);
 fulladder FA7(s6, pp3[2], pp3[3], p[6], c11);
endmodule
10. implementing Booth's multiplication
algorithm:
module booth_mulƟplier (
 input [7:0] mulƟplicand, // 8-bit signed
mulƟplicand
 input [7:0] mulƟplier, // 8-bit signed mulƟplier
 output reg [15:0] product // 16-bit signed
product
);
 reg [7:0] AC; // Accumulator
 reg [7:0] QR; // MulƟplier register
 reg SC; // Sequence counter
 always @(*) begin
 // IniƟalize registers
 AC = 8'b0;
 QR = mulƟplier;
 SC = 4'b0; // 4-bit sequence counter (n/2)
 // Booth's algorithm implementaƟon
 repeat (8) begin
 // Check for the last two bits of QR and SC
 case ({QR[1], QR[0], SC[1], SC[0]})
 // If 00 or 11, no operaƟon
 4'b00, 4'b11: begin
 // Right shiŌ AC and QR
 {AC, QR} = {AC[7], AC, QR[7], QR};
 end
 // If 01, AC = AC + mulƟplicand
 4'b01: begin
 AC = AC + mulƟplicand;
 // Right shiŌ AC and QR
 {AC, QR} = {AC[7], AC, QR[7], QR};
 end
 // If 10, AC = AC - mulƟplicand
 4'b10: begin
 AC = AC - mulƟplicand;
 // Right shiŌ AC and QR
 {AC, QR} = {AC[7], AC, QR[7], QR};
 end
 endcase
 // Right shiŌ SC
 SC = {SC[2], SC[1], QR[0]};
 end
 // Assign the product
 product = {AC, QR};
 end
endmodule
11. Mag. Compaarator Ckt
3bit
module comparator_3bit(
 input [2:0] A, B,
 output c1, c2, c3
);
assign c1 = (A[2] > B[2]) | ((A[2] == B[2]) & ((A[1] >
B[1]) | ((A[1] == B[1]) & (A[0] > B[0]))));
assign c2 = (A[2] == B[2]) & (A[1] == B[1]) & (A[0]
== B[0]);
assign c3 = (A[2] < B[2]) | ((A[2] == B[2]) & ((A[1] <
B[1]) | ((A[1] == B[1]) & (A[0] < B[0]))));
endmodule
module test_comparator;
reg [2:0] A, B;
wire c1, c2, c3;
comparator_3bit dut(
 .A(A),
 .B(B),
 .c1(c1),
 .c2(c2),
 .c3(c3)
);
iniƟal begin
 // Test cases
 A = 3'b000; B = 3'b000; #10;
 A = 3'b010; B = 3'b001; #10;
 A = 3'b101; B = 3'b110; #10;
 // Add more test cases as needed
 $stop;
end
endmodule
4 bit
module comparator_4bit(
 input [3:0] A, B,
 output c1, c2, c3
);
assign c1 = (A > B) ? 1'b1 : 1'b0;
assign c2 = (A < B) ? 1'b1 : 1'b0;
assign c3 = (A == B) ? 1'b1 : 1'b0;
endmodule
module comparator_4bit_test;
reg [3:0] A, B;
wire c1, c2, c3;
comparator_4bit UUT(
 .A(A),
 .B(B),
 .c1(c1),
 .c2(c2),
 .c3(c3)
);
iniƟal begin
 $monitor("A=%b, B=%b, c1=%b, c2=%b, c3=%b",
A, B, c1, c2, c3);
 A = 4'b0000; B = 4'b0000; #10;
 A = 4'b0001; B = 4'b0000; #10;
 A = 4'b0000; B = 4'b0001; #10;
 A = 4'b0001; B = 4'b0001; #10;
 A = 4'b0010; B = 4'b0001; #10;
 A = 4'b0001; B = 4'b0010; #10;
 // Add more test cases if needed
 $finish;
end
endmodule
=========================================
MODULE 5
1. Flip Flop
// Behavioral model of SR Flip Flop
module sr_flip_flop(
 input S, R, CLK,
 output reg Q, Q_bar
);
 always @(posedge CLK) begin
 if (S & ~R)
 Q <= 1'b1;
 else if (~S & R)
 Q <= 1'b0;
 end
 assign Q_bar = ~Q;
endmodule
// Test bench for SR Flip Flop
module test_sr_flip_flop;
 reg S, R, CLK;
 wire Q, Q_bar;
 sr_flip_flop UUT(
 .S(S),
 .R(R),
 .CLK(CLK),
 .Q(Q),
 .Q_bar(Q_bar)
 );
 integer i;
 iniƟal begin
 $monitor("Time=%0t, S=%b, R=%b, CLK=%b,
Q=%b, Q_bar=%b", $Ɵme, S, R, CLK, Q, Q_bar);
 for (i = 0; i < 2; i = i + 1) begin
 S = i % 2; R = 0; CLK = 0; #5;
 S = 1; R = i % 2; CLK = 1; #5;
 S = 0; R = i % 2; CLK = 1; #5;
 S = 0; R = 1; CLK = 1; #5;
 end
 $finish;
 end
endmodule
// Behavioral model of D Flip Flop
module d_flip_flop(
 input D, CLK,
 output reg Q, Q_bar
);
 always @(posedge CLK) begin
 Q <= D;
 end
 assign Q_bar = ~Q;
endmodule
// Test bench for D Flip Flop
module test_d_flip_flop;
 reg D, CLK;
 wire Q, Q_bar;
 d_flip_flop UUT(
 .D(D),
 .CLK(CLK),
 .Q(Q),
 .Q_bar(Q_bar)
 );
 integer i;
 iniƟal begin
 $monitor("Time=%0t, D=%b, CLK=%b, Q=%b,
Q_bar=%b", $Ɵme, D, CLK, Q, Q_bar);
 for (i = 0; i < 2; i = i + 1) begin
 D = i % 2; CLK = 0; #5;
 D = 1; CLK = 1; #5;
 D = 0; CLK = 1; #5;
 D = 1; CLK = 0; #5;
 end
 $finish;
 end
endmodule
// Behavioral model of JK Flip Flop
module jk_flip_flop(
 input J, K, CLK,
 output reg Q, Q_bar
);
 always @(posedge CLK) begin
 if (J & K)
 Q <= ~Q;
 else if (~J & K)
 Q <= 0;
 else if (J & ~K)
 Q <= 1;
 end
 assign Q_bar = ~Q;
endmodule
// Test bench for JK Flip Flop
module test_jk_flip_flop;
 reg J, K, CLK;
 wire Q, Q_bar;
 jk_flip_flop UUT(
 .J(J),
 .K(K),
 .CLK(CLK),
 .Q(Q),
 .Q_bar(Q_bar)
 );
 integer i;
 iniƟal begin
 $monitor("Time=%0t, J=%b, K=%b, CLK=%b,
Q=%b, Q_bar=%b", $Ɵme, J, K, CLK, Q, Q_bar);
 for (i = 0; i < 2; i = i + 1) begin
 J = i % 2; K = 0; CLK = 0; #5;
 J = 1; K = i % 2; CLK = 1; #5;
 J = 0; K = i % 2; CLK = 1; #5;
 J = 0; K = 1; CLK = 1; #5;
 end
 $finish;
 end
endmodule
// Behavioral model of T Flip Flop
module t_flip_flop(
 input T, CLK,
 output reg Q, Q_bar
);
 always @(posedge CLK) begin
 if (T)
 Q <= ~Q;
 end
 assign Q_bar = ~Q;
endmodule
// Test bench for T Flip Flop
module test_t_flip_flop;
 reg T, CLK;
 wire Q, Q_bar;
 t_flip_flop UUT(
 .T(T),
 .CLK(CLK),
 .Q(Q),
 .Q_bar(Q_bar)
 );
 integer i;
 iniƟal begin
 $monitor("Time=%0t, T=%b, CLK=%b, Q=%b,
Q_bar=%b", $Ɵme, T, CLK, Q, Q_bar);
 for (i = 0; i < 2; i = i + 1) begin
 T = i % 2; CLK = 0; #5;
 T = 1; CLK = 1; #5;
 T = 0; CLK = 1; #5;
 T = 1; CLK = 0; #5;
 end
 $finish;
 end
endmodule
2. SHIFT REGISTER
module siso_shiŌ_register(
 input serial_in, clock, reset,
 output reg serial_out
);
 reg [2:0] register;
 always @(posedge clock or posedge reset) begin
 if (reset)
 register <= 3'b0;
 else
 register <= {register[1:0], serial_in};
 end
 assign serial_out = register[0];
endmodule
module sipo_shiŌ_register(
 input serial_in, clock, reset,
 output reg [2:0] parallel_out
);
 reg [2:0] register;
 always @(posedge clock or posedge reset) begin
 if (reset)
 register <= 3'b0;
 else
 register <= {register[1:0], serial_in};
 end
 assign parallel_out = register;
endmodule
module pipo_shiŌ_register(
 input [2:0] parallel_in, clock, reset,
 output reg serial_out
);
 reg [2:0] register;
 always @(posedge clock or posedge reset) begin
 if (reset)
 register <= 3'b0;
 else
 register <= parallel_in;
 end
 assign serial_out = register[0];
endmodule
module piso_shiŌ_register(
 input serial_in, clock, reset,
 output reg [2:0] parallel_out
);
 reg [2:0] register;
 always @(posedge clock or posedge reset) begin
 if (reset)
 register <= 3'b0;
 else
 register <= {serial_in, register[2:1]};
 end
 always @(posedge clock) begin
 if (!reset)
 parallel_out <= register;
 end
endmodule
// Test bench for SISO ShiŌ Register
module test_siso_shiŌ_register;
 reg serial_in, clock, reset;
 wire serial_out;
 siso_shiŌ_register siso_inst(
 .serial_in(serial_in),
 .clock(clock),
 .reset(reset),
 .serial_out(serial_out)
 );
 iniƟal begin
 $monitor("Time=%0t, SerialIn=%b, SerialOut=
%b", $Ɵme, serial_in, serial_out);
 // Test case for SISO ShiŌ Register
 reset = 1;
 serial_in = 1;
 clock = 0;
 #5;
 reset = 0;
 #5;
 serial_in = 0;
 #5;
 serial_in = 1;
 #5;
 $finish;
 end
endmodule
// Test bench for SIPO ShiŌ Register
module test_sipo_shiŌ_register;
 reg serial_in, clock, reset;
 wire [2:0] parallel_out;
 sipo_shiŌ_register sipo_inst(
 .serial_in(serial_in),
 .clock(clock),
 .reset(reset),
 .parallel_out(parallel_out)
 );
 iniƟal begin
 $monitor("Time=%0t, SerialIn=%b,
ParallelOut=%b", $Ɵme, serial_in, parallel_out);
 // Test case for SIPO ShiŌ Register
 reset = 1;
 serial_in = 1;
 clock = 0;
 #5;
 reset = 0;
 #5;
 serial_in = 0;
 #5;
 serial_in = 1;
 #5;
 $finish;
 end
endmodule
// Test bench for PIPO ShiŌ Register
module test_pipo_shiŌ_register;
 reg [2:0] parallel_in, clock, reset;
 wire serial_out;
 pipo_shiŌ_register pipo_inst(
 .parallel_in(parallel_in),
 .clock(clock),
 .reset(reset),
 .serial_out(serial_out)
 );
 iniƟal begin
 $monitor("Time=%0t, ParallelIn=%b,
SerialOut=%b", $Ɵme, parallel_in, serial_out);
 // Test case for PIPO ShiŌ Register
 reset = 1;
 parallel_in = 3'b101;
 clock = 0;
 #5;
 reset = 0;
 #5;
 parallel_in = 3'b010;
 #5;
 parallel_in = 3'b111;
 #5;
 $finish;
 end
endmodule
// Test bench for PISO ShiŌ Register
module test_piso_shiŌ_register;
 reg serial_in, clock, reset;
 wire [2:0] parallel_out;
 piso_shiŌ_register piso_inst(
 .serial_in(serial_in),
 .clock(clock),
 .reset(reset),
 .parallel_out(parallel_out)
 );
 iniƟal begin
 $monitor("Time=%0t, SerialIn=%b,
ParallelOut=%b", $Ɵme, serial_in, parallel_out);
 // Test case for PISO ShiŌ Register
 reset = 1;
 serial_in = 1;
 clock = 0;
 #5;
 reset = 0;
 #5;
 serial_in = 0;
 #5;
 serial_in = 1;
 #5;
 $finish;
 end
endmodule
3. COUNTER
# mod 8 : counter with tb of up and down
module jk_flip_flop(
 input J, K, clk, reset,
 output reg Q, Qbar
);
 always @(posedge clk or posedge reset) begin
 if (reset)
 Q <= 1'b0;
 else begin
 if (J & ~K)
 Q <= 1'b1;
 else if (~J & K)
 Q <= 1'b0;
 end
 end
 assign Qbar = ~Q;
endmodule
module mod8_counter(
 input clk, reset,
 output reg [2:0] Q
);
 reg J, K;
 always @(*) begin
 J = (Q == 3'b111) ? 1'b0 : 1'b1;
 K = (Q == 3'b000) ? 1'b0 : 1'b1;
End
 jk_flip_flop
FF0(.J(J), .K(K), .clk(clk), .reset(reset), .Q(Q[0]), .Qba
r());
 jk_flip_flop
FF1(.J(J), .K(K), .clk(clk), .reset(reset), .Q(Q[1]), .Qba
r());
 jk_flip_flop
FF2(.J(J), .K(K), .clk(clk), .reset(reset), .Q(Q[2]), .Qba
r());
endmodule
module test_mod8_counter;
 reg clk, reset;
 wire [2:0] up_count, down_count;
 mod8_counter up_inst(
 .clk(clk),
 .reset(reset),
 .Q(up_count)
 );
 mod8_counter down_inst(
 .clk(clk),
 .reset(reset),
 .Q(down_count)
 );
 iniƟal begin
 $monitor("Time=%0t, UpCounter=%b,
DownCounter=%b", $Ɵme, up_count,
down_count);
 // Test case for up counter
 reset = 1;
 clk = 0;
 #5 reset = 0;
 #200 reset = 1;
 #5 reset = 0;
 #195;
 // Test case for down counter
 reset = 1;
 clk = 0;
 #5 reset = 0;
 #200 reset = 1;
 #5 reset = 0;
 #195;
 $finish;
 end
endmodule
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