sim

#!/usr/bin/env -S vivado -mode batch -source

create_project -force -part xc7z035ffg900-2 test_tb test_tb

add_files -fileset sources_1 {  \
        ../src/test_1.v     \
        ../src/test_2.v  \
        ../src/test_3.v          \
        ../src/test_4.v             \
        test_tb.sv        \
}

set_property file_type {Verilog}        [get_files *.v]
set_property file_type {SystemVerilog}  [get_files *.sv]

update_compile_order -fileset sources_1
set_property top test_tb [get_fileset sim_1]

launch_simulation -simset sim_1 -mode behavioral
exit