Untitled

def buildSequentialMultiplier(
    aa: Bus,
    bb: Bus,
    loadEnable: Gate
  ): (Gate, Bus) =

    def shiftedA(operandA: Bus): Bus =
      val newBus = operandA.take(operandA.length-1)
      newBus.prepended(operandA.host.False)

    def shiftedB(operandB: Bus): Bus =
      val newBus = operandB.drop(1)
      newBus.appended(operandB.host.False)

    // result min length
    val min_length = aa.length + bb.length

    // host circuit
    val host = loadEnable.host

    // Registers to store operands and result
    val result = host.inputs(min_length)
    val aReg = host.inputs(min_length)
    val bReg = host.inputs(min_length)

    // Create shifted versions of registers
    val aRegShifted = shiftedA(aReg)
    val bRegShifted = shiftedB(bReg)

    // Build the registers based on loadEnable
    // For multiplicand register (aReg)
    for i <- 0 until aa.length do
      val sel = (loadEnable && aa(i)) || (!loadEnable && aRegShifted(i))
      aReg(i).buildFeedbackFrom(sel)

    // For multiplier register (bReg)
    for i <- 0 until bb.length do
      val sel = (loadEnable && bb(i)) || (!loadEnable && bRegShifted(i))
      bReg(i).buildFeedbackFrom(sel)

    // Perform the multiplication with the least significant bit of bReg
    // Add extended mult to result
    val mult = aReg && bReg(0)
    val addition = buildAdder(result, mult)
    result.buildFeedbackFrom(addition && !loadEnable)

    // Check if operation is complete (multiplier is zero)
    // check if this works
    val bIsZero = (~bReg).reduce(_ && _)

    // Ready signal is true when not loading and multiplier is zero
    val ready = !loadEnable && bIsZero

    // Return the ready signal and result bus
    (ready, result)
  end buildSequentialMultiplier