SystemVerilog Testbench for Logic Functions

module tb_common;
logic a, b, en;
wire logic [3:0] zs;
logic [3:0] zs_beh;

// assign_t DUT_1(.A(a), .B(b), .EN(en), .Z(zs));
// primitive_gate DUT_2(.A(a), .B(b), .EN(en), .Z(zs));
 al_t DUT_3(.A(a), .B(b), .EN(en), .Z(zs));

int i,j,k;

initial begin
forever begin
	#5 for(int i=0; i < 2; i++) 
	begin
		#5 for (int j=0; j<2; j++) 
		begin
			#5 for (int k=0; k<2; k++) 
			begin
			en = i;
			a = j;
			b = k;
			#5;
			end
		end
	end
$stop;
end
end

always_comb begin
if (zs_beh !== zs) begin
	$monitor("Error: Output is %4b, but should be %4b", zs, zs_beh," || At time: %d , en,a,b are | %d | %d | %d | output = %4b", $time,en, a, b, zs );
//	$stop;
end
else if (zs_beh === zs) begin
$monitor ("Output matched; At time: %d , en,a,b are | %d | %d | %d | output = %4b", $time,en, a, b, zs);
end
end


always_comb begin
assign zs_beh = (en) ? {~(a & b), ~(a & ~b), ~(~a & b), ~(~a & ~b)} : (en == 0) ? '1: 'z;


end


endmodule