Untitled

module carry_lookahead_adder_pipelined
#(parameter WIDTH = 4, STAGE_WIDTH = 2)
(
    input [WIDTH-1:0] i_add1,
    input [WIDTH-1:0] i_add2,
    input clk,
    input rst,
    output reg [WIDTH-1:0] o_result
);

    wire [WIDTH:0] w_C;
    wire [WIDTH-1:0] w_G, w_P, w_SUM;

    reg [WIDTH-1:0] r_add1 [0:1];
    reg [WIDTH-1:0] r_add2 [0:1];
    reg [WIDTH-1:0] r_SUM [0:1];
    reg [WIDTH:0] r_C [0:1];
    reg [WIDTH-1:0] r_G [0:1];
    reg [WIDTH-1:0] r_P [0:1];
    
    integer ii, jj;

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            for (ii = 0; ii < 2; ii = ii + 1) begin
                r_add1[ii] <= 0;
                r_add2[ii] <= 0;
                r_SUM[ii] <= 0;
                r_C[ii] <= 0;
                r_G[ii] <= 0;
                r_P[ii] <= 0;
            end
        end else begin
            r_add1[0] <= i_add1;
            r_add2[0] <= i_add2;
            for (ii = 1; ii < 2; ii = ii + 1) begin
                r_add1[ii] <= r_add1[ii-1];
                r_add2[ii] <= r_add2[ii-1];
            end
        end
    end

    // Stage 1: Calculate SUM
    generate
        for (ii = 0; ii < WIDTH; ii = ii + 1) begin : GEN_SUM
            assign w_SUM[ii] = r_add1[0][ii] ^ r_add2[0][ii] ^ r_C[0][ii];
        end
    endgenerate

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            for (ii = 0; ii < 2; ii = ii + 1) begin
                r_SUM[ii] <= 0;
            end
        end else begin
            r_SUM[0] <= w_SUM;
            for (ii = 1; ii < 2; ii = ii + 1) begin
                r_SUM[ii] <= r_SUM[ii-1];
            end
        end
    end

    // Stage 2: Calculate Generate and Propagate
    generate
        for (jj = 0; jj < WIDTH; jj = jj + 1) begin : GEN_G_P
            assign w_G[jj] = r_add1[1][jj] & r_add2[1][jj];
            assign w_P[jj] = r_add1[1][jj] | r_add2[1][jj];
        end
    endgenerate

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            for (jj = 0; jj < 2; jj = jj + 1) begin
                r_G[jj] <= 0;
                r_P[jj] <= 0;
            end
        end else begin
            r_G[0] <= w_G;
            r_P[0] <= w_P;
            for (jj = 1; jj < 2; jj = jj + 1) begin
                r_G[jj] <= r_G[jj-1];
                r_P[jj] <= r_P[jj-1];
            end
        end
    end

    // Stage 3: Calculate Carry
    generate
        for (jj = 0; jj < WIDTH; jj = jj + 1) begin : GEN_C
            assign w_C[jj+1] = w_G[jj] | (w_P[jj] & r_C[1][jj]);
        end
    endgenerate

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            for (jj = 0; jj < 2; jj = jj + 1) begin
                r_C[jj] <= 0;
            end
        end else begin
            r_C[0] <= {1'b0, r_SUM[1]};
            for (jj = 1; jj < 2; jj = jj + 1) begin
                r_C[jj] <= r_C[jj-1];
            end
        end
    end

    // Stage 4: Calculate Result
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            o_result <= 0;
        end else begin
            o_result <= r_C[1][WIDTH:1] + r_SUM[1];
        end
    end

endmodule