Untitled

 avatar
unknown
plain_text
a year ago
185 B
6
Indexable
module N_bit_register #(parameter WIDTH = 4) (
    input clk,
    input [WIDTH-1:0] d,
    output reg [WIDTH-1:0] q
);
    always @(posedge clk) begin
        q <= d;
    end
endmodule
Editor is loading...
Leave a Comment