Untitled

`timescale 1ns / 1ps

module LabL4;
    // Declare inputs and output with 32-bit width
    reg [31:0] a0, a1, a2, a3;
    reg [1:0] c;
    wire [31:0] z;

    // Instantiate the 4-to-1 multiplexer
    yMux4to1 #(32) mux4to1(z, a0, a1, a2, a3, c);

    // Testbench variables
    reg [31:0] expected_z;
    integer pass_count, fail_count;

    // Test the multiplexer
    initial begin
        // Initialize counters
        pass_count = 0;
        fail_count = 0;

        // Display header
        $display("c     a0                  a1                  a2                  a3                  | Expected z        Actual z  Result");
        $display("----------------------------------------------------------------------------------------|------------------  ----------  ------");

        // Apply different combinations of random inputs and check results
        repeat (10) begin // Repeat 10 times
            // Generate random 32-bit values for inputs and select lines
            a0 = $random;
            a1 = $random;
            a2 = $random;
            a3 = $random;
            c = $random % 4; // Ensure c is in the range 0 to 3

            // Calculate expected output
            case (c)
                2'b00: expected_z = a0;
                2'b01: expected_z = a1;
                2'b10: expected_z = a2;
                2'b11: expected_z = a3;
                default: expected_z = 32'hx; // Undefined case
            endcase

            #10; // Wait for 10 time units

            // Check if the output is as expected
            if (z === expected_z) begin
                pass_count = pass_count + 1;
                $display("%b %h %h %h %h | %h              %h        PASS", c, a0, a1, a2, a3, expected_z, z);
            end else begin
                fail_count = fail_count + 1;
                $display("%b %h %h %h %h | %h              %h        FAIL", c, a0, a1, a2, a3, expected_z, z);
            end
        end

        // Display summary
        $display("----------------------------------------------------------------------------------------|------------------  ----------  ------");
        $display("Total Tests: %d", pass_count + fail_count);
        $display("Passed: %d", pass_count);
        $display("Failed: %d", fail_count);

        // Finish simulation
        $finish;
    end
endmodule