Untitled

`timescale 1ns / 1ps

module LabL2;
    // Declare inputs as reg and output as wire
    reg [1:0] a, b;
    reg s;
    wire [1:0] y;

    // Instantiate the 2-bit 2-to-1 multiplexer
    yMux2 mux2to1(y, a, b, s);

    // Test the multiplexer
    initial begin
        // Display header
        $display("s  a   b   | y");
        $display("----------|----");

        // Apply different combinations of inputs and display the results
        a = 2'b00; b = 2'b01; s = 0; #10 $display("%b %b %b | %b", s, a, b, y);
        a = 2'b00; b = 2'b01; s = 1; #10 $display("%b %b %b | %b", s, a, b, y);
        a = 2'b10; b = 2'b11; s = 0; #10 $display("%b %b %b | %b", s, a, b, y);
        a = 2'b10; b = 2'b11; s = 1; #10 $display("%b %b %b | %b", s, a, b, y);

        // Finish simulation
        $finish;
    end
endmodule