Untitled

module top_module (
    input clk,
    input in,
    output reg out = 0
);

    wire dout;

    D_ff D_inst(
        .clk(clk),
        .d(in),
        .q(dout)
    );

    always@(posedge clk) begin
        if((!dout) && in)
            out <= 1'b1;
        else 
            out <= 1'b0;
    end


endmodule


module D_ff(
    input clk,
    input d,
    output reg q
);
    always@(posedge clk) begin

        q <= d;

    end

endmodule