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verilog
7 months ago
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`timescale 1ns/100ps

module lab2_1_t();

    parameter DELAY = 5;

    reg clk;
    reg rst_n;
    reg enable;
    reg flip;
    reg [3:0] max;
    reg [3:0] min;
    wire direction;
    wire [3:0] out;

    Parameterized_Ping_Pong_Counter UUT(
        .clk(clk),
        .rst_n(rst_n),
        .enable(enable),
        .flip(flip),
        .max(max),
        .min(min),
        .direction(direction),
        .out(out)
    );

    integer i;
    initial begin
        clk = 0;
        rst_n = 0;
        max = 3'b101;
        min = 3'b000;
        enable = 1;

        #20;
        rst_n = 1;
        #95;
        min = 3'b101;
        #60
        min = 3'b000; 
    end

    always #DELAY clk = !clk;

endmodule