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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY ht_tb IS
END ht_tb;
 
ARCHITECTURE behavior OF ht_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Hardware_transfer_logic_circuit
    PORT(
         B : IN  std_logic_vector(3 downto 0);
         Clr : IN  std_logic;
         Clk : IN  std_logic;
         Load : IN  std_logic;
			RCO: OUT std_logic;
         Output : INOUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal B : std_logic_vector(3 downto 0) := (others => '0');
	signal RCO: std_logic := '0';
   signal Clr : std_logic := '0';
   signal Clk : std_logic := '0';
   signal Load : std_logic := '0';

	--BiDirs
   signal Output : std_logic_vector(3 downto 0):="0000";

   -- Clock period definitions
   constant Clk_period : time := 100 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Hardware_transfer_logic_circuit PORT MAP (
          B => B,
          Clr => Clr,
          Clk => Clk,
          Load => Load,
			 RCO => RCO,
          Output => Output
        );

   -- Clock process definitions
   Clk_process :process
   begin
		Clk <= '0';
		wait for Clk_period/2;
		Clk <= '1';
		wait for Clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      B<="0101";
		Clr<='1';
      Load<='0';
      wait for Clk_period;
      Load<='0';
		wait for Clk_period;
		Load<='1';
      -- insert stimulus here 

      wait;
   end process;

END;