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module ddc(clk,rst,updown,out);
	input clk,rst,updown;
	output [6:0]out;
	wire clkdiv;
	wire [3:0]count;
	frequencydivider u_a(clk,rst,clkdiv);
	counter u_b(rst,updown,clkdiv,count);
	sevendisplay u_c(count,out);
endmodule

module frequencydivider(clk,rst,clkdiv);
	input clk,rst;
	output clkdiv;
	reg [32:0] counter;
	reg clkdiv;

	always @(posedge clk) begin
		if (!rst) begin
			counter <= 32'b0;
			clkdiv <= 1'b0;
		end else begin
         if (counter == 32'd25000000) begin //一秒
            counter <= 25'b0; 
            clkdiv <= ~clkdiv; 
         end else begin
				counter <= counter + 32'd1; 
			end
		end
	end
endmodule


module counter(rst,updown,clkdiv,count);
	input rst,updown,clkdiv;
	output [3:0] count;
	reg [3:0] count;
always @(posedge clkdiv or negedge rst)
	begin
		if(!rst)begin
			count = 0;
		end else begin
		if(updown==0)begin
				count = count - 1;
			end else begin
				count = count + 1;
			end
		end
	end
endmodule

module sevendisplay(count,out);
	input [3:0] count;
	output [6:0] out;
	reg [6:0] out;

always @(count) begin 
	case(count)
		4'b0000: begin
				 out = 7'b1000000;
		end
		4'b0001: begin
				 out = 7'b1111001;
		end
		4'b0010: begin
				 out = 7'b0100100;
		end
		4'b0011: begin
				 out = 7'b0110000;
		end
		4'b0100: begin
				 out = 7'b0011001;
		end
		4'b0101: begin
				 out = 7'b0010010;
		end
		4'b0110: begin
				 out = 7'b0000010;
		end
		4'b0111: begin
				 out = 7'b1111000;
		end
		4'b1000: begin
				 out = 7'b0000000;
		end
		4'b1001: begin
				 out = 7'b0010000;
		end
		4'b1010: begin
				 out = 7'b0001000;
		end
		4'b1011: begin
				 out = 7'b0000011;
		end
		4'b1100: begin
				 out = 7'b1000110;
		end
		4'b1101: begin
				 out = 7'b0100001;
		end
		4'b1110: begin
				 out = 7'b0000110;
		end
		4'b1111: begin
				 out = 7'b0001110;
		end
		default: begin
				 out = 7'b0000000;
		end   
	endcase	
end 
	
endmodule