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`timescale 1ns/10ps module IOTDF( clk, rst, in_en, iot_in, fn_sel, busy, valid, iot_out); input clk; input rst; input in_en; input [7:0] iot_in; input [2:0] fn_sel; output reg busy; output reg valid; output reg [127:0] iot_out; reg [127:0] out_reg, round_reg, sum_reg, outFF12, mux67, outFF3, mux4, mux5; wire co_in, co_ro, co_to; wire [127:0] mxmn_wire1, mxmn_wire2, sum, out4, out5, tol_in; reg128 input_reg(iot_in, clk, in_en,rst, tol_in); counter counting(clk, rst, co_in, co_ro, co_to); //Max&Min maxmin_sel mxmn_sel1(tol_in, round_reg, co_ro, fn_sel, mxmn_wire1); //PeakMax&PeakMin maxmin_sel mxmn_sel2(outFF12, out_reg, co_to, fn_sel, mxmn_wire2); //Average adder add1(tol_in, sum_reg, sum); //Exclude&Extract ext_bool ext(tol_in, out4); exc_bool exc(tol_in, out5); always@(*)begin case(fn_sel) 3'b1:begin iot_out<= outFF12; valid <= 1'b1; //Max end 3'b010:begin iot_out<= outFF12; valid <= 1'b1; //Min end 3'b011:begin iot_out<= outFF3; valid <= 1'b1; //Average end 3'b100:begin iot_out<= mux4; valid <= 1'b1; //Extract //checked end 3'b101:begin iot_out<= mux5; valid <= 1'b1; //Exclude //checked end 3'b110:begin iot_out<= mux67; valid <= 1'b1; //Peak Max end 3'b111:begin iot_out<= mux67; valid <= 1'b1; //Peak Min end default:begin iot_out<=128'b0; end endcase end //DFF always@(posedge clk)begin if(rst)begin busy <= 1'b0; end else if (((fn_sel == 3'b001)&&(co_ro))|| ((fn_sel == 3'b010)&&(co_ro))|| ((fn_sel == 3'b011)&&(co_ro))|| ((fn_sel == 3'b100)&&(co_in))|| ((fn_sel == 3'b101)&&(co_in))|| ((fn_sel == 3'b110)&&(co_to))|| ((fn_sel == 3'b111)&&(co_to))) begin busy <= 1'b1; end else begin busy <= 1'b0; end end always@(posedge co_in)begin round_reg<= mxmn_wire1; sum_reg<=sum; mux4<=out4; mux5<=out5; end always@(posedge co_ro)begin outFF12<= round_reg; out_reg<= mxmn_wire2; outFF3<= {3'b000, sum_reg[127:3]}; end always@(posedge co_to)begin mux67<= out_reg; end endmodule module reg128(cycle_in, clock, enable, rst, in); input [7:0] cycle_in; input clock, rst, enable; output reg [127:0] in; reg [127:0] current_in; reg [3:0] count; always@(posedge clock)begin if(rst|(!enable))begin count<=3'b0; end else if (count==4'd15)begin in<=current_in; end else begin current_in<={current_in[119:0], cycle_in}; count<=count+1; end end endmodule module counter(clock, reset, count16, count128, count1536); input clock, reset; output reg count16, count128, count1536; reg [10:0] count; always@(*)begin if((count[3:0]==4'd0)&& (count[6:0]!=7'd0)&& (count!=11'b11000000000)) begin count1536<=1'b0; count128<=1'b0; count16<=1'b1; end else if ((count[3:0]==4'd0)&& (count[6:0]==7'd0)&& (count!=11'b11000000000)) begin count1536<=1'b0; count128<=1'b1; count16<=1'b1; end else if ((count[3:0]==4'd0)&& (count[6:0]==7'd0)&& (count==11'b11000000000)) begin count1536<=1'b1; count128<=1'b1; count16<=1'b1; end else begin count1536<=1'b0; count128<=1'b0; count16<=1'b0; end end always@(posedge clock) if(reset||(count==11'b11000000000)) count<=11'b1; else count<=count+1; endmodule module comparator_notsmaller(in1, in2, notsmaller); input [127:0] in1, in2; output reg notsmaller; always@(*) notsmaller=(in1>=in2); endmodule module maxmin_sel(totalin, roundreg, round_rst, fnsel, mux_wire); input round_rst; input [127:0] totalin, roundreg; input [2:0] fnsel; output reg [127:0] mux_wire; reg mmsel; wire cmp; comparator_notsmaller cmp0(totalin, roundreg, cmp); always@(*)begin mmsel<=(((!cmp)&fnsel[1]&fnsel[0])|((!cmp)&(!fnsel[2])&fnsel[1])|(cmp&fnsel[2]&(!fnsel[0]))|(cmp&(!fnsel[1]))); if(mmsel||round_rst) mux_wire<= totalin; else mux_wire<= roundreg; end endmodule module ext_bool(in4, out4); input [127:0] in4; output reg [127:0] out4; reg match; always@(*)begin match<= ((in4[127]&(!in4[126])&(!in4[125]))|(!in4[127])&in4[126]&in4[125]&in4[124]); if(match) out4<= in4; else out4<= 128'b0; end endmodule module exc_bool(in5, out5); input [127:0] in5; output reg [127:0] out5; reg match; always@(*)begin match<= ((in5[127]&in5[126])|((!in5[127])&(!in5[126]))|(in5[126]&(!in5[124]))|(in5[126]&(!in5[125]))); if(match) out5<= in5; else out5<= 128'b0; end endmodule module adder(inreg, sumreg, sum); input [127:0] inreg, sumreg; output reg [127:0] sum; always@(*) sum<= inreg+ sumreg; endmodule //ncverilog IOTDF1.v -c
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