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`timescale 1ns / 1ps

module DataMemSys_tb;

    // Inputs
    reg clk;
    reg rst;
    reg MemRead;
    reg MemWrite;
    reg [9:0] addr;
    reg [31:0] data_in;

    // Outputs
    wire [31:0] data_out;
    wire stall;

    // Instantiate the Unit Under Test (UUT)
    DataMemSys uut (
        .clk(clk),
        .rst(rst),
        .MemRead(MemRead),
        .MemWrite(MemWrite),
        .addr(addr),
        .data_in(data_in),
        .data_out(data_out),
        .stall(stall)
    );

    // Clock generation
    initial begin
        clk = 0;
        forever #5 clk = !clk; // Clock with a period of 10 ns
    end

    // Test sequence
    initial begin
        // Initialize Inputs
        rst = 1;
        MemRead = 0;
        MemWrite = 0;
        addr = 0;
        data_in = 0;

        // Reset pulse
        #10;
        rst = 0;
        #10;
        rst = 1;
        #20;

        // Write Data to memory
        MemWrite = 1;
        addr = 10'h3FA;
        data_in = 32'hDEADBEEF;
        #10;
        MemWrite = 0;
        #10;

        // Read Data from memory
        MemRead = 1;
        addr = 10'h3FA;
        #10;
        MemRead = 0;
        #10;

        // End of simulation
        $finish;
    end

endmodule
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