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#include "p18f4520.inc" ; CONFIG1H CONFIG OSC = INTIO67 ; Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7) CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) CONFIG IESO = OFF ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled) ; CONFIG2L CONFIG PWRT = OFF ; Power-up Timer Enable bit (PWRT disabled) CONFIG BOREN = SBORDIS ; Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) CONFIG BORV = 3 ; Brown Out Reset Voltage bits (Minimum setting) ; CONFIG2H CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit)) CONFIG WDTPS = 32768 ; Watchdog Timer Postscale Select bits (1:32768) ; CONFIG3H CONFIG CCP2MX = PORTC ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) CONFIG PBADEN = ON ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset) CONFIG LPT1OSC = OFF ; Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation) CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled) ; CONFIG4L CONFIG STVREN = ON ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled) CONFIG XINST = OFF ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) ; CONFIG5L CONFIG CP0 = OFF ; Code Protection bit (Block 0 (000800-001FFFh) not code-protected) CONFIG CP1 = OFF ; Code Protection bit (Block 1 (002000-003FFFh) not code-protected) CONFIG CP2 = OFF ; Code Protection bit (Block 2 (004000-005FFFh) not code-protected) CONFIG CP3 = OFF ; Code Protection bit (Block 3 (006000-007FFFh) not code-protected) ; CONFIG5H CONFIG CPB = OFF ; Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) CONFIG CPD = OFF ; Data EEPROM Code Protection bit (Data EEPROM not code-protected) ; CONFIG6L CONFIG WRT0 = OFF ; Write Protection bit (Block 0 (000800-001FFFh) not write-protected) CONFIG WRT1 = OFF ; Write Protection bit (Block 1 (002000-003FFFh) not write-protected) CONFIG WRT2 = OFF ; Write Protection bit (Block 2 (004000-005FFFh) not write-protected) CONFIG WRT3 = OFF ; Write Protection bit (Block 3 (006000-007FFFh) not write-protected) ; CONFIG6H CONFIG WRTC = OFF ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) CONFIG WRTB = OFF ; Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected) CONFIG WRTD = OFF ; Data EEPROM Write Protection bit (Data EEPROM not write-protected) ; CONFIG7L CONFIG EBTR0 = OFF ; Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) CONFIG EBTR1 = OFF ; Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) CONFIG EBTR2 = OFF ; Table Read Protection bit (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks) CONFIG EBTR3 = OFF ; Table Read Protection bit (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks) ; CONFIG7H CONFIG EBTRB = OFF ; Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks) Counter EQU 0x00 ORG 0x00 GOTO Start ISR: org 0x08 MOVLW 0x03 CPFSGT Counter GOTO State1 MOVLW 0x07 CPFSGT Counter GOTO State2 MOVLW 0x0F CPFSGT Counter GOTO State3 State1: MOVLW d'61' MOVWF PR2 GOTO Done State2: MOVLW d'122' MOVWF PR2 GOTO Done State3: MOVLW d'244' MOVWF PR2 GOTO Done Done: INCF Counter INCF LATA BCF PIR1, TMR2IF MOVLW 0x10 CPFSLT Counter CLRF Counter RETFIE Start: MOVLW 0xFF MOVWF ADCON1 CLRF TRISA CLRF LATA BSF RCON, IPEN BSF INTCON, GIE BCF PIR1, TMR2IF BSF IPR1, TMR2IP BSF PIE1, TMR2IE MOVLW 0xFF MOVWF T2CON MOVLW d'244' ;0.25*4s MOVWF PR2 MOVLW d'00100000' MOVWF OSCCON CLRF Counter Main: BRA Main end
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