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package acal_lab04.Lab

import chisel3._
import chisel3.util._
import chisel3.util.log2Ceil


class MultiShareBus(val addrWidth: Int,val dataWidth: Int,val numMasters: Int,val numSlaves: Int, val addrMap: Seq[(Int, Int)]) extends Module {
  val io = IO(new Bundle {
    val masters = Vec(numMasters, Flipped(Decoupled(new MasterInterface(addrWidth, dataWidth))))
    val slaves = Vec(numSlaves, Decoupled(new SlaveInterface(addrWidth, dataWidth)))
  })
    // decoder
    val decoders = Seq.tabulate(numSlaves) { i =>
      Module(new Decoder(addrWidth, addrMap.slice(i, i+1)))
    }

    // initialize the ready signal
    for(i <- 0 until numMasters){
      io.masters(i).ready   := false.B
    }

    // // two master arbiter (round robin)
    // // use one bit to record which master is last granted
    val lastGrant       = RegInit(0.U(1.W))   
    val tranDone        = Wire(Bool())
    val request         = Wire(Bool())

    // OR all valid signals from masters
    request := io.masters.map(_.valid).reduce(_ || _)          
    // the arbiter is idle (no request) or previous transaction has done 
    tranDone:= !request || io.masters(lastGrant).valid && io.masters(lastGrant).ready 

    when(request && tranDone){
      lastGrant := ~lastGrant
    }
    io.masters(lastGrant).ready := io.slaves.map(_.ready).reduce(_ || _)   // OR all ready signals

    // Initialize signals
    for (i <- 0 until numSlaves) {
      io.slaves(i).valid      := io.masters(lastGrant).valid && decoders(i).io.select
      io.slaves(i).bits.addr  := io.masters(lastGrant).bits.addr
      io.slaves(i).bits.data  := io.masters(lastGrant).bits.data
      io.slaves(i).bits.size  := io.masters(lastGrant).bits.size
      decoders(i).io.addr     := io.masters(lastGrant).bits.addr
    }

}