Untitled
unknown
plain_text
6 months ago
5.6 kB
1
Indexable
Never
/* PARALLEL ADDER AND SUBTRACTOR module fulladder(a,b,ic,o,oc); input a,b,ic; output o,oc; assign o = (~ic & ((a & ~b) | (~a & b)) ) | (ic & ~((a & ~b) | (~a & b)) ); assign oc = (a & b) | (b & ic) | (ic & a); endmodule module main(in1,in2,ic,out,oc); input [3:0]in1; input [3:0]in2; input ic; output [3:0]out; output [3:0]oc; fulladder fa1(in1[0],in2[0],ic,out[0],oc[0]); fulladder fa2(in1[1],in2[1],oc[0],out[1],oc[1]); fulladder fa3(in1[2],in2[2],oc[1],out[2],oc[2]); fulladder fa4(in1[3],in2[3],oc[2],out[3],oc[3]); endmodule Test Bench module adder_tb; wire [3:0]oc; wire [3:0]out; reg [3:0]in1; reg [3:0]in2; reg ic; main m(in1,in2,ic,out,oc); initial begin in1=4'b1010; in2=4'b1001; ic=0; end endmodule */ 4×1 MUX in behavioral modeling: module m41 ( a, b, c, d, s0, s1, out); input wire a, b, c, d; input wire s0, s1; output reg out; always @ (a or b or c or d or s0, s1) begin case (s0 | s1) 2'b00 : out <= a; 2'b01 : out <= b; 2'b10 : out <= c; 2'b11 : out <= d; endcase end endmodule module top; wire out; reg a; reg b; reg c; reg d; reg s0, s1; m41 name(.out(out), .a(a), .b(b), .c(c), .d(d), .s0(s0), .s1(s1)); initial begin a=1'b0; b=1'b0; c=1'b0; d=1'b0; s0=1'b0; s1=1'b0; #500 $finish; end always #40 a=~a; always #20 b=~b; always #10 c=~c; always #5 d=~d; always #80 s0=~s0; always #160 s1=~s1; always@(a or b or c or d or s0 or s1) $monitor("At time = %t, Output = %d", $time, out); endmodule; Behavioral Modelling module T_FF(Q,QB,T,CLK); input T,CLK; output Q,QB; reg Q=0,QB; always @(posedge CLK) begin case(T) 1'b0:Q=Q; 1'b1:Q=~Q; endcase QB=~Q; end endmodule Test Bench module T_FF_TB; reg T; reg CLK; wire Q; wire QB; T_FF uut (.Q(Q), .QB(QB), .T(T),.CLK(CLK)); always #100 CLK=~CLK; initial begin CLK=1; #200 T=0; #200 T=1; #200 T=0; #200 T=1; end endmodule // Decoder 2 to 4 DISClAIMER:: In below codes : for output we use nand and ~ sign because of this circuit work when enable = en = 0.. If we take en = 1 for working than no need to take nand and ~ sign. 1. Behavioral Modeling: module decoder24_behaviour(en,a,b,y); // input port input en,a,b; // use reg to store the output value output reg [3:0]y; // always is used in design block // only in Behavioural modeling. always @(en,a,b) begin // using condition if statement // implement the 2:4 truth table if(en==0) begin if(a==1'b0 & b==1'b0) y=4'b1110; else if(a==1'b0 & b==1'b1) y=4'b1101; else if(a==1'b1 & b==1'b0) y=4'b1011; else if(a==1 & b==1) y=4'b0111; else y=4'bxxxx; end else y=4'b1111; end endmodule Testbench: Behavioral Modeling: module tb; // input port are declared in reg(register) reg a,b,en; // output port are declared in wire(net) wire [3:0]y; // instantiate design block decoder24_behaviour dut(en,a,b,y); initial begin $monitor("en=%b a=%b b=%b y=%b",en,a,b,y); // with reference to truth table provide input values en=1;a=1'bx;b=1'bx;#5 en=0;a=0;b=0;#5 en=0;a=0;b=1;#5 en=0;a=1;b=0;#5 en=0;a=1;b=1;#5 // terminate simulation using $finish system task $finish; end endmodule 2. Data Flow Modeling: module decoder24_assign(en,a,b,y); // declare input and output ports input en,a,b; output [3:0]y; // supportive connection required wire enb,na,nb; assign enb = ~en; assign na = ~a; assign nb = ~b; // assign output value by referring to logic diagram assign y[0] = ~(enb&na&nb); assign y[1] = ~(enb&na&b); assign y[2] = ~(enb&a&nb); assign y[3] = ~(enb&a&b); endmodule TestBench: Data Flow: module tb; // input port are declared in reg(register) reg a,b,en; // output port are declared in wire(net) wire [3:0]y; // instantiate design block decoder24_assign dut(en,a,b,y); initial begin $monitor("en=%b a=%b b=%b y=%b",en,a,b,y); // with reference to truth // table provide input values en=1;a=1'bx;b=1'bx;#5 en=0;a=0;b=0;#5 en=0;a=0;b=1;#5 en=0;a=1;b=0;#5 en=0;a=1;b=1;#5 // terminate simulation using $finish system task $finish; end endmodule 3. Gate Level Modeling: module decoder24_gate(en,a,b,y); // declare input and output ports input en,a,b; output [3:0]y; // supportive connections required // to connect nand gates wire enb,na,nb; // instantiate 4 nand gates and 3 not gates // make connections by referring the above logic diagram not n0(enb,en); not n1(na,a); not n2(nb,b); nand n3(y[0],enb,na,nb); nand n4(y[1],enb,na,b); nand n5(y[2],enb,a,nb); nand n6(y[3],enb,a,b); endmodule Testbench: Gate Level: module tb; // input port are declared in reg(register) reg a,b,en; // output port are declared in wire(net) wire [3:0]y; // instantiate design block decoder24_gate dut(en,a,b,y); initial begin $monitor("en=%b a=%b b=%b y=%b",en,a,b,y); // with reference to truth table provide input values en=1;a=1'bx;b=1'bx;#5 en=0;a=0;b=0;#5 en=0;a=0;b=1;#5 en=0;a=1;b=0;#5 en=0;a=1;b=1;#5 // terminate simulation using $finish system task $finish; end endmodule