Untitled

module DataMemSys ( 
    input clk,
    input rst,
    input MemRead,
    input MemWrite,
    input [9:0] addr,
    input [31:0] data_in,
    output [31:0] data_out,
    output stall);
    
    wire[1:0] offset = addr [1:0];
    wire [4:0]index = addr [6:2];
    wire [2:0]tag = addr[9:7];
    wire [127:0] MsData_out;
    wire fill;
    wire update;
    wire MsReady;
    wire MsRead;
    
    DataCache cache (
        clk,
        update,
        fill,
        offset,
        index,
        data_in,
        data_out, //OUTPUT
        MsData_out );
    
    DataMem_updated DM_N (
        clk,
        MsRead,
        MemWrite,
        addr,
        data_in,
        MsData_out, //OUTPUT
        MsReady);   //OUPUT
    
    DataCacheController cont(
        clk,
        rst,
        MemRead,
        MemWrite, 
        index,
        tag,
        stall,  //OUTPUT
        fill,   //OUTPUT
        update, //OUTPUT
        MsRead, //OUTPUT
        MsReady);


endmodule