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module test (clk,rst,in,out);
	input clk,rst,in;
	output [6:0]out;
	wire clkdiv;
	wire [3:0]count;
	frequencydivider u_a(clk,rst,clkdiv);
	counter u_b(rst,clkdiv,in,count);
	sevendisplay u_c(count,out);
endmodule
module frequencydivider(clk,rst,clkdiv);//讓clock每一秒從0變1 1變0
	input clk,rst;
	output clkdiv;
	reg [32:0] counter;
	reg clkdiv;

	always @(posedge clk) begin
		if (!rst) begin
			counter <= 32'b0;
			clkdiv <= 1'b0;
		end else begin
         if (counter == 32'd25000000) begin //一秒
            counter <= 25'b0; 
            clkdiv <= ~clkdiv; 
         end else begin
				counter <= counter + 32'd1; 
			end
		end
	end
endmodule
module counter(rst,clkdiv,in,count);
	input rst,clkdiv,in;
	output [3:0] count;
	reg [3:0]cur,next;
	reg [3:0]count;
	parameter st0=4'b0000,
				 st1=4'b0001,
				 st2=4'b0010,
				 st3=4'b0011,
				 st4=4'b0100,
				 st5=4'b0101;
always @(posedge clkdiv or negedge rst)
	begin
		if(!rst)begin
			cur<=st0;
		end else begin
			cur<=next;			
		end	
	end
	
always @(in or cur)
	begin 
		next<=st0;
	case(cur)
		st0: if(in==1)
				next<=st3;
			  else
				next<=st1;
		st1: if(in==1)
				next<=st5;
			  else
				next<=st2;
		st2: if(in==1)
				next<=st0;
			  else
				next<=st3;
		st3: if(in==1)
				next<=st1;
			  else
				next<=st4;				
		st4: if(in==1)
				next<=st2;
			  else
				next<=st5;		
		st5: if(in==1)
				next<=st4;
			  else
				next<=st0;
	endcase
	end
always@(cur)begin
	case(cur)
		st0: count<=4'b0000;
      st1: count<=4'b0001;
		st2: count<=4'b0010;
		st3: count<=4'b0011;
		st4: count<=4'b0100;
		st5: count<=4'b0101;	
	endcase
end
	
endmodule
module sevendisplay(count,out);
	input [3:0] count;
	output [6:0] out;
	reg [6:0] out;

always @(count) begin 
	case(count)
		4'b0000:out = 7'b1000000;

		4'b0001:out = 7'b1111001;

		4'b0010:out = 7'b0100100;

		4'b0011:out = 7'b0110000;

		4'b0100:out = 7'b0011001;

		4'b0101:out = 7'b0010010;
		
		default:out = 7'b0000000;
  
	endcase	
end 
	
endmodule 
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