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#include <xc.h> #include<stdio.h> #include<stdlib.h> #include <time.h> #define _XTAL_FREQ 1000000 #pragma config OSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled) // CONFIG2L #pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled) #pragma config BOREN = ON // Brown-out Reset Enable bits (Brown-out Reset enabled and controlled by software (SBOREN is enabled)) #pragma config BORV = 3 // Brown Out Reset Voltage bits (Minimum setting) // CONFIG2H #pragma config WDT = OFF // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit)) #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) // CONFIG3H #pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) #pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset) #pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation) #pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled) // CONFIG4L #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) #pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled) #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) // CONFIG5L #pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-001FFFh) not code-protected) #pragma config CP1 = OFF // Code Protection bit (Block 1 (002000-003FFFh) not code-protected) #pragma config CP2 = OFF // Code Protection bit (Block 2 (004000-005FFFh) not code-protected) #pragma config CP3 = OFF // Code Protection bit (Block 3 (006000-007FFFh) not code-protected) // CONFIG5H #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) // CONFIG6L #pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-001FFFh) not write-protected) #pragma config WRT1 = OFF // Write Protection bit (Block 1 (002000-003FFFh) not write-protected) #pragma config WRT2 = OFF // Write Protection bit (Block 2 (004000-005FFFh) not write-protected) #pragma config WRT3 = OFF // Write Protection bit (Block 3 (006000-007FFFh) not write-protected) // CONFIG6H #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected) #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) // CONFIG7L #pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) #pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) #pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks) #pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks) // CONFIG7H #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks) #pragma config OSC = INTIO67 //OSCILLATOR SELECTION BITS (INTERNAL OSCILLATOR BLOCK, PORT FUNCTION ON RA6 AND RA7) #pragma config WDT = OFF //Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit)) #pragma config PWRT = OFF //Power-up Timer Enable bit (PWRT disabled) #pragma config BOREN = ON //Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) #pragma config PBADEN = OFF //PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset) #pragma config LVP = OFF //Single-Supply ICSP Enable bit (Single-Supply ICSP disabled) #pragma config CPD = OFF //Data EEPROM Code Protection bit (Data EEPROM not code-protected) void __interrupt(high_priority)H_ISR(){ //step4 int value = (ADRESH<<2)|(ADRESL>>6) ; value = (int)(value/(1024/64)); CCPR1L = value>>2; CCP1CONbits.DC1B = value%4; __delay_ms(1); //do things //clear flag bit PIR1bits.ADIF = 0; ADCON0bits.GO = 1; //step5 & go back step3 /* delay at least 2tad ADCON0bits.GO = 1; */ return; } void main(void) { //configure OSC and port OSCCONbits.IRCF = 0b100; //1MHz TRISAbits.RA0 = 1; //analog input port //step1 ADCON1bits.VCFG0 = 0; ADCON1bits.VCFG1 = 0; ADCON1bits.PCFG = 0b1110; //AN0 ?analog input,???? digital ADCON0bits.CHS = 0b0000; //AN0 ?? analog input ADCON2bits.ADCS = 0b000; //????000(1Mhz < 2.86Mhz) ADCON2bits.ACQT = 0b001; //Tad = 2 us acquisition time?2Tad = 4 > 2.4 ADCON0bits.ADON = 1; //enable A/D ADCON2bits.ADFM = 0; //left justified //step2 PIE1bits.ADIE = 1; //enable A/D interrupt PIR1bits.ADIF = 0; //clear A/D interrupt bit INTCONbits.PEIE = 1; //enable peripheral interrupt INTCONbits.GIE = 1; //enable interrupt //step3 ADCON0bits.GO = 1; //set go/done bit //init TRISC = 0; LATC = 0; T2CONbits.TMR2ON = 0b1; T2CONbits.T2CKPS = 0b01; // Internal Oscillator Frequency, Fosc = 125 kHz, Tosc = 8 ?s OSCCONbits.IRCF = 0b001; // PWM mode, P1A, P1C active-high; P1B, P1D active-high CCP1CONbits.CCP1M = 0b1100; // CCP1/RC2 -> Output TRISC = 0; LATC = 0; // Set up PR2, CCP to decide PWM period and Duty Cycle /** * PWM period * = (PR2 + 1) * 4 * Tosc * (TMR2 prescaler) * = (0x9b + 1) * 4 * 8?s * 4 * = 0.019968s ~= 20ms */ PR2 = 0x9b; /** * Duty cycle * = (CCPR1L:CCP1CON<5:4>) * Tosc * (TMR2 prescaler) * = (0x0b*4 + 0b01) * 8?s * 4 * = 0.00144s ~= 1450?s */ // CCPR1L = 8; // CCP1CONbits.DC1B = 0; while(1); return; }
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