Untitled
unknown
plain_text
4 years ago
1.0 kB
8
Indexable
module full_adder(in0, in1, cin, out, cout);
input in0, in1, cin;
output out, cout;
wire wire1, wire2, wire3;
xor xor1(wire1, in0, in1);
and and1(wire2, wire1, cin);
and and2(wire3, in0, in1);
xor xor2(out, wire1, cin);
or or1(cout, wire2, wire3);
endmodule
module ripple_carry_adder (in0, in1, out, cout,s_overflow,u_overflow);
// declare input signals
input [3:0] in0;
input [3:0] in1;
// declare output signals
output [3:0] out;
output cout;
output s_overflow;
output u_overflow;
// here is your design
wire [3:0] in0, in1;
wire c1, c2, c3;
wire [3:0] out;
wire cout, s_overflow, u_overflow;
full_adder f0(in0[0], in1[0], 0, out[0], c1);
full_adder f1(in0[1], in1[1], c1, out[1], c2);
full_adder f2(in0[2], in1[2], c2, out[2], c3);
full_adder f3(in0[3], in1[3], c3, out[3], cout);
xor xor1(s_overflow, cout, c3);
or or1(u_overflow, cout);
endmodule
Editor is loading...