Untitled

mail@pastecode.io avatar
unknown
verilog
7 months ago
1.5 kB
3
Indexable
Never
`timescale 1ps/1ps

module clock_divider
    #(parameter n = 25)(
    input clk,
    output clk_div
    );
    reg[n-1:0]num;
    wire[n-1:0]next_num;
    always@(posedge clk)begin
        num <= next_num;
    end
    assign next_num = num + 1;
    assign clk_div = num[n-1];
endmodule

module lab3_1(
    input clk,
    input rst,
    input en,
    input speed,
    output reg [15:0] led
);
// add your design here
wire clk_div0, clk_div1, clk_div25, clk_div27;
reg [2:0] state;
reg [2:0] next_state;

clock_divider #(25) div1(.clk(clk), .clk_div(clk_div25));
clock_divider #(27) div2(.clk(clk), .clk_div(clk_div27));

assign clk_div0 = (speed)? clk_div25 : clk_div27;

always @(posedge clk_div0 or posedge rst) begin
    if(rst)
        state <= 0;
    else
        state <= next_state;
end

always @(*) begin
    if(state == 3'b100)
        next_state = 0;
    else
        next_state = state + 1;
end

always @(posedge clk_div0 or posedge rst) begin
    if(rst) begin
        led <= 0;
    end 
    else begin
        if (en) begin
            case (state)
                3'b000: led <= 16'b0000000000000000;
                3'b001: led <= 16'b1000100010001000;
                3'b010: led <= 16'b1100110011001100;
                3'b011: led <= 16'b1110111011101110;
                3'b100: led <= 16'b1111111111111111;
                default: led <= 16'b0000000000000000; 
            endcase
        end
        else
            led <= led;
    end
end

endmodule