Untitled

Library ieee;
use ieee.std_logic_1164.all;

Entity simple is
port (x, Reset, cl: in std_logic;
 z: out std_logic);
end simple;

architecture Behavioral of simple is
Subtype states is std_logic_vector (1 downto 0);
constant A: states:="00";
constant B: states:="01";
constant C: states:="10";
signal state: states;
begin
 process (cl, Reset)
begin
 if (cl'event and cl='1') then
 If Reset='1' then
 state<=A;
else
case state is
when A => if (x='0') then
 state<=A;
 z<='0';
 else
state<=B;
 z<='0';
 end if;
when B => if (x='0') then
 state<=A;
 z<='0';
 else
 state<=C;
 z<='0';
 end if;
when C => if (x='0') then
 state<=A;
 z<='1';
 else
 state<=C;
 z<='0';
 end if;
when others=>null;
end case;
end if;
end if;
end process;
end Behavioral;