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---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:41:16 02/22/2024 -- Design Name: -- Module Name: jk_ff - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity jk_ff is Port ( j : in STD_LOGIC; k : in STD_LOGIC; clk : in STD_LOGIC; Q : out STD_LOGIC; Q2 : out STD_LOGIC); end jk_ff; architecture Behavioral of jk_ff is begin process(j, k, clk) begin if(clk = '1') then if(j /= k) then Q <= k; Q2 <= j; end if; end if; end process; end Behavioral;
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