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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SevenSegmentControl is
Port (
clk : in STD_LOGIC;
key1, key2, key3, key4 : in STD_LOGIC;
seven_segment : out STD_LOGIC_VECTOR (6 downto 0)
);
end SevenSegmentControl;
architecture Behavioral of SevenSegmentControl is
signal digit : STD_LOGIC_VECTOR (3 downto 0) := "0000"; -- 4-digit binary counter
signal display_data : STD_LOGIC_VECTOR (6 downto 0);
-- 7-segment display truth table for digits 0-4
constant seven_segment_data : STD_LOGIC_VECTOR (15 downto 0) := "1000000", -- 0
"1111001", -- 1
"0100100", -- 2
"0110000", -- 3
"0011001", -- 4
others => "0000000";
begin
-- Increment the digit on rising edge of the clock
process (clk)
begin
if rising_edge(clk) then
if key1 = '1' then
digit <= "0001"; -- Display 1 at units place
elsif key2 = '1' then
digit <= "0010"; -- Display 2 at tens place
elsif key3 = '1' then
digit <= "0100"; -- Display 3 at hundreds place
elsif key4 = '1' then
digit <= "1000"; -- Display 4 at thousands place
else
digit <= "0000"; -- Display off when no key is pressed
end if;
end if;
end process;
-- Assign display_data based on the digit to be displayed
process (digit)
begin
case digit is
when "0001" =>
display_data <= seven_segment_data(0);
when "0010" =>
display_data <= seven_segment_data(1);
when "0100" =>
display_data <= seven_segment_data(2);
when "1000" =>
display_data <= seven_segment_data(3);
when others =>
display_data <= "0000000"; -- Display off for unknown digit
end case;
end process;
-- Output the display_data to the seven-segment display
seven_segment <= display_data;
end Behavioral;Editor is loading...