程式碼
unknown
verilog
3 years ago
384 B
12
Indexable
//ex3 module lab9ex3(seg,dig,key); input [6:1]key; output reg[7:0]seg; output reg[7:0]dig; reg [3:0]value; //key[3] = add, key[6] = reset always@(negedge key[3] or negedge key[6]) begin if(~key[6]) value <= 0; else if(~key[3]) value <= (value == 9)? 0 : value + 1; end //seg always @(*) begin case(value) //case statement endcase end endmodule
Editor is loading...