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module decoder_hex_16 (
input [3:0] x,
output reg [0:6] h
);
always @(*) begin
case (x)
4'h0: h = 7'b0000001;
4'h1: h = 7'b1001111;
4'h2: h = 7'b0010010;
4'h3: h = 7'b0000110;
4'h4: h = 7'b1001100;
4'h5: h = 7'b0100100;
4'h6: h = 7'b0100000;
4'h7: h = 7'b0001111;
4'h8: h = 7'b0000000;
4'h9: h = 7'b0000100;
4'hA: h = 7'b0001000;
4'hB: h = 7'b1100000;
4'hC: h = 7'b0110001;
4'hD: h = 7'b1000010;
4'hE: h = 7'b0110000;
4'hF: h = 7'b0111000;
endcase
end
endmodule
module full_adder (
input a, b, cin,
output s, cout
);
assign s = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (a & cin);
endmodule
module adder_N_bits #(
parameter N = 8
)(
input [N-1:0] A, B,
input cin,
output [N-1:0] S,
output cout
);
wire [N:0] c;
assign c[0] = cin;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : adder_loop
full_adder fa (
.a(A[i]), .b(B[i]),
.cin(c[i]),
.s(S[i]),
.cout(c[i+1])
);
end
endgenerate
assign cout = c[N];
endmodule
module register_N_bits_ena_aclr #(
parameter N = 8
)(
input clk,
input aclr,
input ena,
input [N-1:0] D,
output reg [N-1:0] Q
);
always @(posedge clk, negedge aclr)
if (!aclr)
Q <= {N{1'b0}};
else if (ena)
Q <= D;
endmodule
create_clock -period 20.000 -name clk clk
zad 1
module accum_N_bits_top (
input [7:0] SW,
input [1:0] KEY,
output [9:0] LEDR,
output [0:6] HEX0,
output [0:6] HEX1,
output [0:6] HEX2,
output [0:6] HEX3
);
wire clk = KEY[1];
wire aclr = KEY[0];
reg [7:0] S;
wire [7:0] sum;
wire carry;
wire overflow;
// Wersja 1 - sumator strukturalny
adder_N_bits #(.N(8)) adder (
.A(S),
.B(SW),
.cin(1'b0),
.S(sum),
.cout(carry)
);
assign overflow = (S[7] == SW[7]) && (sum[7] != S[7]);
always @(posedge clk, negedge aclr)
if (!aclr)
S <= 8'd0;
else
S <= sum;
assign LEDR[7:0] = S;
assign LEDR[8] = carry;
assign LEDR[9] = overflow;
decoder_hex_16 dec_a1 (.x(SW[7:4]), .h(HEX3));
decoder_hex_16 dec_a0 (.x(SW[3:0]), .h(HEX2));
decoder_hex_16 dec_s1 (.x(S[7:4]), .h(HEX1));
decoder_hex_16 dec_s0 (.x(S[3:0]), .h(HEX0));
endmodule
wersja 2
module accum_N_bits_top (
input [7:0] SW,
input [1:0] KEY,
output [9:0] LEDR,
output [0:6] HEX0,
output [0:6] HEX1,
output [0:6] HEX2,
output [0:6] HEX3
);
wire clk = KEY[1];
wire aclr = KEY[0];
reg [7:0] S;
wire [7:0] sum;
wire carry;
wire overflow;
// Wersja 2 - prosty assign zamiast strukturalnego sumatora
assign {carry, sum} = S + SW;
assign overflow = (S[7] == SW[7]) && (sum[7] != S[7]);
always @(posedge clk, negedge aclr)
if (!aclr)
S <= 8'd0;
else
S <= sum;
assign LEDR[7:0] = S;
assign LEDR[8] = carry;
assign LEDR[9] = overflow;
decoder_hex_16 dec_a1 (.x(SW[7:4]), .h(HEX3));
decoder_hex_16 dec_a0 (.x(SW[3:0]), .h(HEX2));
decoder_hex_16 dec_s1 (.x(S[7:4]), .h(HEX1));
decoder_hex_16 dec_s0 (.x(S[3:0]), .h(HEX0));
endmodule
zad 2
module accum_N_bits_top (
input [7:0] SW,
input [1:0] KEY,
output [9:0] LEDR,
output [0:6] HEX0,
output [0:6] HEX1,
output [0:6] HEX2,
output [0:6] HEX3
);
wire clk = KEY[1];
wire aclr = KEY[0];
reg [7:0] S;
wire [7:0] sum;
wire carry;
wire overflow;
// Wersja 2 - prosty assign zamiast strukturalnego sumatora
assign {carry, sum} = S + SW;
assign overflow = (S[7] == SW[7]) && (sum[7] != S[7]);
always @(posedge clk, negedge aclr)
if (!aclr)
S <= 8'd0;
else
S <= sum;
assign LEDR[7:0] = S;
assign LEDR[8] = carry;
assign LEDR[9] = overflow;
decoder_hex_16 dec_a1 (.x(SW[7:4]), .h(HEX3));
decoder_hex_16 dec_a0 (.x(SW[3:0]), .h(HEX2));
decoder_hex_16 dec_s1 (.x(S[7:4]), .h(HEX1));
decoder_hex_16 dec_s0 (.x(S[3:0]), .h(HEX0));
endmodule
zadanie 3
module array_multiplier_4_bits (
input [3:0] A,
input [3:0] B,
output [7:0] P
);
// Czesciowe iloczyny
wire [3:0] pp0, pp1, pp2, pp3;
assign pp0 = {4{B[0]}} & A;
assign pp1 = {4{B[1]}} & A;
assign pp2 = {4{B[2]}} & A;
assign pp3 = {4{B[3]}} & A;
// Sumowanie z odpowiednim przesunieciem
wire [7:0] partial1 = {4'b0, pp0} + {3'b0, pp1, 1'b0};
wire [7:0] partial2 = partial1 + {2'b0, pp2, 2'b0};
assign P = partial2 + {1'b0, pp3, 3'b0};
endmodule
module array_multiplier_top (
input [7:0] SW,
output [0:6] HEX0,
output [0:6] HEX2,
output [0:6] HEX4,
output [0:6] HEX5
);
wire [3:0] A = SW[7:4];
wire [3:0] B = SW[3:0];
wire [7:0] P;
array_multiplier_4_bits mult (.A(A), .B(B), .P(P));
decoder_hex_16 dec_a (.x(A), .h(HEX2));
decoder_hex_16 dec_b (.x(B), .h(HEX0));
decoder_hex_16 dec_p1 (.x(P[7:4]), .h(HEX5));
decoder_hex_16 dec_p0 (.x(P[3:0]), .h(HEX4));
endmodule
zadanie 4
module multiplier_N_bits #(
parameter N = 8
)(
input [N-1:0] A, B,
output [2*N-1:0] P
);
assign P = A * B;
endmodule
module multiplier_top (
input CLOCK_50,
input [9:0] SW,
input [0:0] KEY,
output [9:0] LEDR,
output [0:6] HEX0,
output [0:6] HEX1,
output [0:6] HEX2,
output [0:6] HEX3
);
wire aclr = KEY[0];
wire EA = SW[9];
wire EB = SW[8];
wire [7:0] Data = SW[7:0];
wire [7:0] A, B;
wire [15:0] P_combo;
reg [15:0] P;
register_N_bits_ena_aclr #(.N(8)) reg_A (
.clk(CLOCK_50), .aclr(aclr),
.ena(EA), .D(Data), .Q(A)
);
register_N_bits_ena_aclr #(.N(8)) reg_B (
.clk(CLOCK_50), .aclr(aclr),
.ena(EB), .D(Data), .Q(B)
);
multiplier_N_bits #(.N(8)) mult (
.A(A), .B(B), .P(P_combo)
);
always @(posedge CLOCK_50, negedge aclr)
if (!aclr)
P <= 16'd0;
else
P <= P_combo;
assign LEDR[7:0] = EA ? A : (EB ? B : 8'd0);
assign LEDR[9:8] = 2'b00;
decoder_hex_16 dec0 (.x(P[3:0]), .h(HEX0));
decoder_hex_16 dec1 (.x(P[7:4]), .h(HEX1));
decoder_hex_16 dec2 (.x(P[11:8]), .h(HEX2));
decoder_hex_16 dec3 (.x(P[15:12]), .h(HEX3));
endmodule
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