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module counter_modulo_k_top (
    input  [2:0] KEY,
    output [9:0] LEDR
);
    wire [4:0] Q;
    wire rollover;

    counter_modulo_k #(.k(25)) counter (
        .clk(KEY[0]),
        .aclr(KEY[1]),
        .enable(KEY[2]),
        .Q(Q),
        .rollover(rollover)
    );

    assign LEDR[4:0] = Q;
    assign LEDR[8:5] = 4'b0000;
    assign LEDR[9] = rollover;

endmodule

module counter_modulo_k #(
    parameter k = 25
)(
    input  clk,
    input  aclr,
    input  enable,
    output reg [N-1:0] Q,
    output rollover
);
    function integer clogb2(input [31:0] v);
        for (clogb2 = 0; v > 0; clogb2 = clogb2 + 1)
            v = v >> 1;
    endfunction

    localparam N = clogb2(k - 1);

    always @(posedge clk, negedge aclr)
        if (!aclr)
            Q <= {N{1'b0}};
        else if (enable) begin
            if (Q == k - 1)
                Q <= {N{1'b0}};
            else
                Q <= Q + 1'b1;
        end

    assign rollover = (Q == k - 1) ? 1'b1 : 1'b0;

endmodule

z2
module delay_01_sec (
    input  clk,
    input  aclr,
    output E
);
    counter_modulo_k #(.k(5000000)) cnt (
        .clk(clk),
        .aclr(aclr),
        .enable(1'b1),
        .Q(),
        .rollover(E)
    );
endmodule

module counter_BCD_3_digits (
    input  CLOCK_50,
    input  [0:0] KEY,
    output [0:6] HEX0,
    output [0:6] HEX1,
    output [0:6] HEX2,
    output [0:0] LEDR
);
    wire aclr;
    wire tick_01s;
    wire rollover0, rollover1, rollover2;
    wire [3:0] d0, d1, d2;
    wire enable_d1, enable_d2;

    assign aclr = KEY[0];

    delay_01_sec delay (.clk(CLOCK_50), .aclr(aclr), .E(tick_01s));

    counter_modulo_k #(.k(10)) cnt0 (
        .clk(CLOCK_50), .aclr(aclr),
        .enable(tick_01s),
        .Q(d0), .rollover(rollover0)
    );

    assign enable_d1 = tick_01s & rollover0;
    counter_modulo_k #(.k(10)) cnt1 (
        .clk(CLOCK_50), .aclr(aclr),
        .enable(enable_d1),
        .Q(d1), .rollover(rollover1)
    );

    assign enable_d2 = tick_01s & rollover0 & rollover1;
    counter_modulo_k #(.k(10)) cnt2 (
        .clk(CLOCK_50), .aclr(aclr),
        .enable(enable_d2),
        .Q(d2), .rollover(rollover2)
    );

    assign LEDR[0] = (d2 == 4'd9) && (d1 == 4'd9) && (d0 == 4'd9);

    decoder_hex_16 dec0 (.x(d0), .h(HEX0));
    decoder_hex_16 dec1 (.x(d1), .h(HEX1));
    decoder_hex_16 dec2 (.x(d2), .h(HEX2));

endmodule

module decoder_hex_16 (
    input  [3:0] x,
    output reg [0:6] h
);
    always @(*) begin
        case (x)
            4'h0: h = 7'b0000001;
            4'h1: h = 7'b1001111;
            4'h2: h = 7'b0010010;
            4'h3: h = 7'b0000110;
            4'h4: h = 7'b1001100;
            4'h5: h = 7'b0100100;
            4'h6: h = 7'b0100000;
            4'h7: h = 7'b0001111;
            4'h8: h = 7'b0000000;
            4'h9: h = 7'b0000100;
            4'hA: h = 7'b0001000;
            4'hB: h = 7'b1100000;
            4'hC: h = 7'b0110001;
            4'hD: h = 7'b1000010;
            4'hE: h = 7'b0110000;
            4'hF: h = 7'b0111000;
        endcase
    end
endmodule

z3

module delay_10ms (
    input  clk,
    input  aclr,
    output E
);
    counter_modulo_k #(.k(500000)) cnt (
        .clk(clk), .aclr(aclr),
        .enable(1'b1),
        .Q(), .rollover(E)
    );
endmodule

module real_time_clock (
    input  CLOCK_50,
    input  [7:0] SW,
    input  [3:0] KEY,
    output [0:6] HEX0,
    output [0:6] HEX1,
    output [0:6] HEX2,
    output [0:6] HEX3,
    output [0:6] HEX4,
    output [0:6] HEX5
);
    reg [3:0] cc0, cc1;
    reg [3:0] ss0, ss1;
    reg [3:0] mm0, mm1;
    wire tick_10ms;
    wire start = KEY[0];
    wire load_cc = ~KEY[3];
    wire load_ss = ~KEY[2];
    wire load_mm = ~KEY[1];

    delay_10ms delay (.clk(CLOCK_50), .aclr(1'b1), .E(tick_10ms));

    wire time_not_zero = (cc0 != 0) || (cc1 != 0) ||
                        (ss0 != 0) || (ss1 != 0) ||
                        (mm0 != 0) || (mm1 != 0);

    always @(posedge CLOCK_50) begin
        if (load_cc) begin
            cc0 <= SW[3:0];
            cc1 <= SW[7:4];
        end else if (load_ss) begin
            ss0 <= SW[3:0];
            ss1 <= SW[7:4];
        end else if (load_mm) begin
            mm0 <= SW[3:0];
            mm1 <= SW[7:4];
        end else if (start && tick_10ms && time_not_zero) begin
            if (cc0 != 0)
                cc0 <= cc0 - 1'b1;
            else begin
                cc0 <= 4'd9;
                if (cc1 != 0)
                    cc1 <= cc1 - 1'b1;
                else begin
                    cc1 <= 4'd9;
                    if (ss0 != 0)
                        ss0 <= ss0 - 1'b1;
                    else begin
                        ss0 <= 4'd9;
                        if (ss1 != 0)
                            ss1 <= ss1 - 1'b1;
                        else begin
                            ss1 <= 4'd5;
                            if (mm0 != 0)
                                mm0 <= mm0 - 1'b1;
                            else begin
                                mm0 <= 4'd9;
                                if (mm1 != 0)
                                    mm1 <= mm1 - 1'b1;
                            end
                        end
                    end
                end
            end
        end
    end

    decoder_hex_16 d0 (.x(cc0), .h(HEX0));
    decoder_hex_16 d1 (.x(cc1), .h(HEX1));
    decoder_hex_16 d2 (.x(ss0), .h(HEX2));
    decoder_hex_16 d3 (.x(ss1), .h(HEX3));
    decoder_hex_16 d4 (.x(mm0), .h(HEX4));
    decoder_hex_16 d5 (.x(mm1), .h(HEX5));

endmodule
z4
module blinking_leds (
    input  CLOCK_50,
    input  [0:0] KEY,
    output [7:0] LEDR
);
    wire aclr;
    wire tick_05s, tick_1s;
    reg leds_05s;
    reg leds_1s;

    assign aclr = KEY[0];

    // Generator impulsow co 0.5 s (50 MHz / 2 Hz = 25 000 000)
    counter_modulo_k #(.k(25000000)) gen_05s (
        .clk(CLOCK_50), .aclr(aclr),
        .enable(1'b1),
        .Q(), .rollover(tick_05s)
    );

    // Generator impulsow co 1 s (50 MHz / 1 Hz = 50 000 000)
    counter_modulo_k #(.k(50000000)) gen_1s (
        .clk(CLOCK_50), .aclr(aclr),
        .enable(1'b1),
        .Q(), .rollover(tick_1s)
    );

    always @(posedge CLOCK_50, negedge aclr)
        if (!aclr)
            leds_05s <= 1'b0;
        else if (tick_05s)
            leds_05s <= ~leds_05s;

    always @(posedge CLOCK_50, negedge aclr)
        if (!aclr)
            leds_1s <= 1'b0;
        else if (tick_1s)
            leds_1s <= ~leds_1s;

    assign LEDR[3:0] = {4{leds_05s}};
    assign LEDR[7:4] = {4{leds_1s}};

endmodule