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module pipelined_carry_lookahead_adder #(parameter WIDTH = 4) (
    input clk,
    input [WIDTH-1:0] i_add1,
    input [WIDTH-1:0] i_add2,
    output [WIDTH:0] o_result
);
    wire [WIDTH-1:0] w_SUM_stage1, w_SUM_stage2;
    wire [WIDTH:0] w_C, w_C_stage2;
    wire [WIDTH-1:0] w_G, w_P;

    // Stage 1: Full Adders
    genvar ii;
    generate
        for (ii = 0; ii < WIDTH; ii = ii + 1) begin
            assign w_SUM_stage1[ii] = i_add1[ii] ^ i_add2[ii] ^ w_C[ii];
        end
    endgenerate

    // Register to hold intermediate sum values
    N_bit_register #(WIDTH) reg_stage1 (.clk(clk), .d(w_SUM_stage1), .q(w_SUM_stage2));

    // Stage 2: Generate and Propagate Terms
    generate
        for (ii = 0; ii < WIDTH; ii = ii + 1) begin
            assign w_G[ii] = i_add1[ii] & i_add2[ii];
            assign w_P[ii] = i_add1[ii] | i_add2[ii];
        end
    endgenerate

    // Stage 3: Carry Terms
    generate
        for (ii = 0; ii < WIDTH; ii = ii + 1) begin
            assign w_C[ii + 1] = w_G[ii] | (w_P[ii] & w_C[ii]);
        end
    endgenerate

    // Register to hold intermediate carry values
    N_bit_register #(WIDTH) reg_stage2 (.clk(clk), .d(w_C[WIDTH-1:0]), .q(w_C_stage2[WIDTH-1:0]));

    assign w_C[0] = 1'b0; // No carry input on first adder
    assign w_C_stage2[WIDTH] = w_G[WIDTH-1] | (w_P[WIDTH-1] & w_C_stage2[WIDTH-1]);
    assign o_result = {w_C_stage2[WIDTH], w_SUM_stage2}; // Verilog Concatenation

endmodule
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