Untitled

module logic_gate(a, b, and_out, or_out, not_out, xor_out, xnor_out);
    input a, b;
    output and_out, or_out, not_out, xor_out, xnor_out;

    wire nand_ab, nand_a, nand_b;
    wire t1, t2, t3;

    
    assign nand_ab = ~(a & b);

    
    assign not_out = ~(a & a);

   
    assign and_out = ~(nand_ab & nand_ab);

    
    assign nand_a = ~(a & a);
    assign nand_b = ~(b & b);
    assign or_out = ~(nand_a & nand_b);

    
    assign t1 = ~(a & b);
    assign t2 = ~(a & t1);
    assign t3 = ~(b & t1);
    assign xor_out = ~(t2 & t3);

   
    assign xnor_out = ~(xor_out & xor_out);

endmodule

module logic_gates_tb;
    wire and_y, or_y, not_y, xor_y, xnor_y;
    reg t_a, t_b;

    logic_gate my_gate (
        .a(t_a), 
        .b(t_b), 
        .and_out(and_y), 
        .or_out(or_y),
        .not_out(not_y),		
        .xor_out(xor_y), 
        .xnor_out(xnor_y) 
    );

    initial begin
        
        $display("\n===== AND GATE =====");
        $display("A B | AND");

        t_a=0; t_b=0; #5; $display("%b %b | %b", t_a, t_b, and_y);
        t_a=0; t_b=1; #5; $display("%b %b | %b", t_a, t_b, and_y);
        t_a=1; t_b=0; #5; $display("%b %b | %b", t_a, t_b, and_y);
        t_a=1; t_b=1; #5; $display("%b %b | %b", t_a, t_b, and_y);

        $display("\n===== OR GATE =====");
        $display("A B | OR");

        t_a=0; t_b=0; #5; $display("%b %b | %b", t_a, t_b, or_y);
        t_a=0; t_b=1; #5; $display("%b %b | %b", t_a, t_b, or_y);
        t_a=1; t_b=0; #5; $display("%b %b | %b", t_a, t_b, or_y);
        t_a=1; t_b=1; #5; $display("%b %b | %b", t_a, t_b, or_y);

        $display("\n===== NOT GATE =====");
        $display("A | NOT");

        t_a=0; #5; $display("%b | %b", t_a, not_y);
        t_a=1; #5; $display("%b | %b", t_a, not_y);

        $display("\n===== XOR GATE =====");
        $display("A B | XOR");

        t_a=0; t_b=0; #5; $display("%b %b | %b", t_a, t_b, xor_y);
        t_a=0; t_b=1; #5; $display("%b %b | %b", t_a, t_b, xor_y);
        t_a=1; t_b=0; #5; $display("%b %b | %b", t_a, t_b, xor_y);
        t_a=1; t_b=1; #5; $display("%b %b | %b", t_a, t_b, xor_y);

        $display("\n===== XNOR GATE =====");
        $display("A B | XNOR");

        t_a=0; t_b=0; #5; $display("%b %b | %b", t_a, t_b, xnor_y);
        t_a=0; t_b=1; #5; $display("%b %b | %b", t_a, t_b, xnor_y);
        t_a=1; t_b=0; #5; $display("%b %b | %b", t_a, t_b, xnor_y);
        t_a=1; t_b=1; #5; $display("%b %b | %b", t_a, t_b, xnor_y);

        $finish;
    end
endmodule