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# Define input and output ports explicitly
set ports_a [get_ports a]
set ports_b [get_ports b]
set ports_sum [get_ports sum]
set ports_carry [get_ports carry]

# Input delay constraints (Assuming external signals arrive with a delay)
set_input_delay 2 -clock [get_clocks clk] $ports_a
set_input_delay 2 -clock [get_clocks clk] $ports_b

# Output delay constraints (Assuming external setup requirements)
set_output_delay 2 -clock [get_clocks clk] $ports_sum
set_output_delay 2 -clock [get_clocks clk] $ports_carry

# False path (Optional: If necessary to ignore specific paths in timing analysis)
set_false_path -from $ports_a -to $ports_carry