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verilog
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module processor_with_ROM_auto (
    input         CLOCK_50,
    input  [9:0]  SW,
    output [9:0]  LEDR,
    output [0:6]  HEX0,
    output [0:6]  HEX1
);
    wire Resetn = ~SW[0];   // SW0 dol = Resetn=1 (dzialanie), SW0 gora = reset
    wire Run    = SW[9];    // SW9 gora = Run=1
    
    // Dzielnik dla PClock - 4 Hz (krok co 0.25 s)
    reg [23:0] p_counter;
    reg PClock;
    always @(posedge CLOCK_50, negedge Resetn) begin
        if (!Resetn) begin
            p_counter <= 0;
            PClock <= 0;
        end
        else if (p_counter == 6250000 - 1) begin
            p_counter <= 0;
            PClock <= ~PClock;
        end
        else
            p_counter <= p_counter + 1;
    end
    
    // MClock - wolniejszy, taktuje co 4 cykle PClock
    // (1 cykl pobierania + max 3 cykle wykonania add/sub)
    reg [2:0] m_counter;
    reg MClock;
    always @(posedge PClock, negedge Resetn) begin
        if (!Resetn) begin
            m_counter <= 0;
            MClock <= 0;
        end
        else if (m_counter == 4 - 1) begin
            m_counter <= 0;
            MClock <= ~MClock;
        end
        else
            m_counter <= m_counter + 1;
    end
    
    wire [4:0] addr;
    wire [8:0] data_rom;
    wire [8:0] BusWires;
    wire Done;
    
    counter5 cnt (
        .clk(MClock),
        .resetn(Resetn),
        .count(addr)
    );
    
    rom32x9 rom (
        .address(addr),
        .clock(MClock),
        .q(data_rom)
    );
    
    proc cpu (
        .DIN(data_rom),
        .Resetn(Resetn),
        .Clock(PClock),
        .Run(Run),
        .Done(Done),
        .BusWires(BusWires)
    );
    
    assign LEDR[8:0] = BusWires;
    assign LEDR[9] = Done;
    
    // Wyswietlanie aktualnego adresu na HEX0-1
    decoder_hex_16 dec_addr_hi (.x({3'b000, addr[4]}), .h(HEX1));
    decoder_hex_16 dec_addr_lo (.x(addr[3:0]),         .h(HEX0));
endmodule
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