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`timescale 1ps/1ps

module clock_divider
    #(parameter n = 25)(
    input clk,
    output clk_div
    );

    reg[n-1:0]num;
    wire[n-1:0]next_num;

    always@(posedge clk)begin
        num <= next_num;
    end

    assign next_num = num + 1;
    assign clk_div = num[n-1];

endmodule

module lab3_1 (
    input clk,
    input rst,
    input en,
    input speed,
    output reg [15:0] led
    );
    
    wire clk_div_25, clk_div_27;
    clock_divider #(25) div1(.clk(clk), .clk_div(clk_div_25));
    clock_divider #(27) div2(.clk(clk), .clk_div(clk_div_27));

    assign clk_used = (speed) ? clk_div_25 : clk_div_27;

    // Use a counter to deal with the light;
    reg [2:0] cnt, nxt_cnt;
    always @(posedge clk_used) begin
        cnt <= nxt_cnt;
    end

    always @(*) begin
        if(cnt == 3'b100) nxt_cnt = 0;
        else nxt_cnt = cnt + 1;
    end

    // For output
    reg [15:0] nxt_led;
    always @(posedge clk_used, posedge rst) begin
        if(rst) begin
            led <= 16'b0000000000000000;
        end
        else begin
            if(en) begin
                // Ctrl the led
                case(cnt) 
                    3'b000: led <= 16'b0000000000000000;
                    3'b001: led <= 16'b1000100010001000;
                    3'b010: led <= 16'b1100110011001100;
                    3'b011: led <= 16'b1110111011101110;
                    3'b100: led <= 16'b1111111111111111;
                    default: led <= led;
                endcase
            end
            else led <= led;
        end
    end

endmodule