Untitled

library IEEE;
use IEEE.std_logic_1164.all;

ENTITY seven_segment_dec IS
   PORT (b0,b1,b2,b3,V) : IN std_logic;
         a : OUT std_logic_vector(6 downto 0));
END seven_segment_dec;

ARCHITECTURE behavioral OF seven_segment_dec IS
begin
  a(0) <= (b1 and not b2 and not b3) or (not b0 and not b1 and not b2 and b3) when V='1' else '0';
  a(1) <= (b1 and b2 and not b3) or (b1 and not b2 and b3) when V='1' else '0';
  a(2) <= (not b1 and b2 and not b3) when V='1' else '0';
  a(3) <= (b1 and not b2 and not b3) or
          (not b0 and not b1 and not b2 and b3) or
          (b1 and b2 and b3) when V='1' else '0';
  a(4) <= (b1 and not b2) or b3 when V='1' else '0';
  a(5) <= (not b1 and b2) or (not b0 and not b1 and b3) or (b2 and b3) when V='1' else '0';
  a(6) <= (b1 and b2 and b3) or (not b0 and not b1 and not b2) when V='1' else '0';
END behavioral;