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// Code your design here
module register_m
#(
  	parameter int unsigned W = 1 // Width
 )
 ( 
    output logic [W-1:0] q    , // register data output
    input  logic [W-1:0] d    , // data input
    input  logic         enb  , // enable
    input  logic         rst_ , // reset (asynch low)
    input  logic         clk    // clock
 ) ;

    timeunit        1ns ;
    timeprecision 100ps ;
  
    //continue aqui
    always_ff @(posedge clk or negedge rst_)
    begin
      if(!rst_)
        if(enb)
        	q<=d;
      	else
          	q<=q
      else
        q<=0;
    end

endmodule : register_m
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