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LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY qsys_lab_custom_component IS
    PORT (
        clock, resetn : IN STD_LOGIC;
        read, write, chipselect : IN STD_LOGIC;
        address : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        writedata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
        readdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
        segments1, segments2, segments3, segments4 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
    );
END qsys_lab_custom_component;

ARCHITECTURE Structure OF qsys_lab_custom_component IS
    COMPONENT gNN_ARCCOS_DISPLAY
    PORT (
        clock, resetn : IN STD_LOGIC;
        input_value : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        segments1, segments2, segments3, segments4 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
    );
    END COMPONENT;

    SIGNAL input_value : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
    input_value <= writedata(7 DOWNTO 0);

    gNN_ARCCOS_DISPLAY_inst : gNN_ARCCOS_DISPLAY PORT MAP (
        clock => clock,
        resetn => resetn,
        input_value => input_value,
        segments1 => segments1,
        segments2 => segments2,
        segments3 => segments3,
        segments4 => segments4
    );

    readdata <= (OTHERS => '0'); -- default read data value

END Structure;