Untitled

`timescale 1ns / 1ps

module LabL3;
    // Declare inputs as reg and output as wire with 32-bit width
    reg [31:0] a, b;
    reg c;
    wire [31:0] z;

    // Instantiate the 32-bit 2-to-1 multiplexer
    yMux #(32) my_mux(z, a, b, c);

    // Test the multiplexer
    initial begin
        // Display header
        $display("c       a                   b                   | z");
        $display("-------------------------------------------------|------------------------------");

        // Apply different combinations of random inputs and display the results
        repeat (10) begin // Repeat 10 times
            // Generate random 32-bit values and a random select signal
            a = $random;
            b = $random;
            c = $random % 2; // Ensure c is 0 or 1

            #10; // Wait for 10 time units

            // Display the current values and result
            $display("%b %h %h | %h", c, a, b, z);
        end

        // Finish simulation
        $finish;
    end
endmodule