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LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY qsys_lab_custom_component IS
    PORT (
        clock, resetn : IN STD_LOGIC;
        read, write, chipselect : IN STD_LOGIC;
        address : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        writedata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
        readdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
        segments1, segments2, segments3, segments4 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
    );
END qsys_lab_custom_component;

ARCHITECTURE Structure OF qsys_lab_custom_component IS
    COMPONENT g55_ARCCOS_DISPLAY
	Port (CLOCK: in std_logic;
			X : in std_logic_vector(7 downto 0);
			HEX0: out std_logic_vector(6 downto 0);
			HEX1: out std_logic_vector(6 downto 0);
			HEX2: out std_logic_vector(6 downto 0);
			HEX3: out std_logic_vector(6 downto 0)
		);

    END COMPONENT;
	 
begin

process(clock, writedata)

BEGIN
	assignments: g55_ARCCOS_DISPLAY port map(clock => CLOCK, HEX0 => segments1, HEX1=>segments2, HEX2=>segments3, HEX3=>segments4);
	
	if rising_edge(clock) then 
	
		if (writedata = 1) then 
		
			write_data <= writedata(7 downto 0);
			
		end if;
	
	end if;
end process;
end Structure;