--------------------
Cycle 1:
IF Unit:
Waiting:
Executed:
Pre-Issue Queue:
Entry 0: [add x1, x0, x0]
Entry 1: [addi x2, x0, #3]
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 0 0 0 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 2:
IF Unit:
Waiting: [beq x1, x2, #22]
Executed:
Pre-Issue Queue:
Entry 0: [addi x2, x0, #3]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue: [add x1, x0, x0]
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 0 0 0 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 3:
IF Unit:
Waiting: [beq x1, x2, #22]
Executed:
Pre-Issue Queue:
Entry 0: [addi x2, x0, #3]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue: [add x1, x0, x0]
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 0 0 0 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 4:
IF Unit:
Waiting: [beq x1, x2, #22]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue: [addi x2, x0, #3]
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 0 0 0 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 5:
IF Unit:
Waiting: [beq x1, x2, #22]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue: [addi x2, x0, #3]
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 0 0 0 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 6:
IF Unit:
Waiting: [beq x1, x2, #22]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 0 0 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 7:
IF Unit:
Waiting:
Executed: [beq x1, x2, #22]
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 0 0 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 8:
IF Unit:
Waiting:
Executed:
Pre-Issue Queue:
Entry 0: [sll x6, x1, #2]
Entry 1: [lw x3, 312(x6)]
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 0 0 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 9:
IF Unit:
Waiting:
Executed:
Pre-Issue Queue:
Entry 0: [lw x3, 312(x6)]
Entry 1: [lw x4, 324(x6)]
Entry 2: [add x5, x3, x4]
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue: [sll x6, x1, #2]
Post-ALU3 Queue:
Registers
x00: 0 0 3 0 0 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 10:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [lw x3, 312(x6)]
Entry 1: [lw x4, 324(x6)]
Entry 2: [add x5, x3, x4]
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue: [sll x6, x1, #2]
Registers
x00: 0 0 3 0 0 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 11:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [lw x3, 312(x6)]
Entry 1: [lw x4, 324(x6)]
Entry 2: [add x5, x3, x4]
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 0 0 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 12:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [lw x4, 324(x6)]
Entry 1: [add x5, x3, x4]
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0: [lw x3, 312(x6)]
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 0 0 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 13:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [add x5, x3, x4]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0: [lw x4, 324(x6)]
Entry 1:
Pre-MEM Queue: [lw x3, 312(x6)]
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 0 0 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 14:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [add x5, x3, x4]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue: [lw x4, 324(x6)]
Post-MEM Queue: [lw x3, 312(x6)]
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 0 0 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 15:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [add x5, x3, x4]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue: [lw x4, 324(x6)]
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 -1 0 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 16:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [add x5, x3, x4]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 -1 1 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 17:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue: [add x5, x3, x4]
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 -1 1 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 18:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue: [add x5, x3, x4]
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 -1 1 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 19:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 -1 1 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 20:
IF Unit:
Waiting:
Executed: [blt x5, x0, #6]
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 -1 1 0 0 0
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 21:
IF Unit:
Waiting:
Executed: [jal x7, #4]
Pre-Issue Queue:
Entry 0: [sub x5, x3, x4]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 -1 1 0 0 296
x08: 0 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 22:
IF Unit:
Waiting:
Executed: [jal x8, #-20]
Pre-Issue Queue:
Entry 0: [addi x1, x1, #1]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue: [sub x5, x3, x4]
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 -1 1 0 0 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 23:
IF Unit:
Waiting: [beq x1, x2, #22]
Executed:
Pre-Issue Queue:
Entry 0: [addi x1, x1, #1]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue: [sub x5, x3, x4]
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 -1 1 0 0 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 24:
IF Unit:
Waiting: [beq x1, x2, #22]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue: [addi x1, x1, #1]
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 -1 1 -2 0 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 25:
IF Unit:
Waiting: [beq x1, x2, #22]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue: [addi x1, x1, #1]
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 0 3 -1 1 -2 0 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 26:
IF Unit:
Waiting: [beq x1, x2, #22]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -1 1 -2 0 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 27:
IF Unit:
Waiting:
Executed: [beq x1, x2, #22]
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -1 1 -2 0 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 28:
IF Unit:
Waiting:
Executed:
Pre-Issue Queue:
Entry 0: [sll x6, x1, #2]
Entry 1: [lw x3, 312(x6)]
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -1 1 -2 0 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 29:
IF Unit:
Waiting:
Executed:
Pre-Issue Queue:
Entry 0: [lw x3, 312(x6)]
Entry 1: [lw x4, 324(x6)]
Entry 2: [add x5, x3, x4]
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue: [sll x6, x1, #2]
Post-ALU3 Queue:
Registers
x00: 0 1 3 -1 1 -2 0 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 30:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [lw x3, 312(x6)]
Entry 1: [lw x4, 324(x6)]
Entry 2: [add x5, x3, x4]
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue: [sll x6, x1, #2]
Registers
x00: 0 1 3 -1 1 -2 0 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 31:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [lw x3, 312(x6)]
Entry 1: [lw x4, 324(x6)]
Entry 2: [add x5, x3, x4]
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -1 1 -2 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 32:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [lw x4, 324(x6)]
Entry 1: [add x5, x3, x4]
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0: [lw x3, 312(x6)]
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -1 1 -2 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 33:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [add x5, x3, x4]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0: [lw x4, 324(x6)]
Entry 1:
Pre-MEM Queue: [lw x3, 312(x6)]
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -1 1 -2 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 34:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [add x5, x3, x4]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue: [lw x4, 324(x6)]
Post-MEM Queue: [lw x3, 312(x6)]
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -1 1 -2 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 35:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [add x5, x3, x4]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue: [lw x4, 324(x6)]
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -2 1 -2 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 36:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [add x5, x3, x4]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -2 2 -2 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 37:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue: [add x5, x3, x4]
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -2 2 -2 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 38:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue: [add x5, x3, x4]
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -2 2 -2 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 39:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -2 2 0 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 40:
IF Unit:
Waiting:
Executed: [blt x5, x0, #6]
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -2 2 0 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 41:
IF Unit:
Waiting:
Executed: [jal x7, #4]
Pre-Issue Queue:
Entry 0: [sub x5, x3, x4]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -2 2 0 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 42:
IF Unit:
Waiting:
Executed: [jal x8, #-20]
Pre-Issue Queue:
Entry 0: [addi x1, x1, #1]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue: [sub x5, x3, x4]
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -2 2 0 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 43:
IF Unit:
Waiting: [beq x1, x2, #22]
Executed:
Pre-Issue Queue:
Entry 0: [addi x1, x1, #1]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue: [sub x5, x3, x4]
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -2 2 0 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 44:
IF Unit:
Waiting: [beq x1, x2, #22]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue: [addi x1, x1, #1]
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -2 2 -4 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 45:
IF Unit:
Waiting: [beq x1, x2, #22]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue: [addi x1, x1, #1]
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 1 3 -2 2 -4 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 46:
IF Unit:
Waiting: [beq x1, x2, #22]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -2 2 -4 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 47:
IF Unit:
Waiting:
Executed: [beq x1, x2, #22]
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -2 2 -4 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 48:
IF Unit:
Waiting:
Executed:
Pre-Issue Queue:
Entry 0: [sll x6, x1, #2]
Entry 1: [lw x3, 312(x6)]
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -2 2 -4 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 49:
IF Unit:
Waiting:
Executed:
Pre-Issue Queue:
Entry 0: [lw x3, 312(x6)]
Entry 1: [lw x4, 324(x6)]
Entry 2: [add x5, x3, x4]
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue: [sll x6, x1, #2]
Post-ALU3 Queue:
Registers
x00: 0 2 3 -2 2 -4 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 50:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [lw x3, 312(x6)]
Entry 1: [lw x4, 324(x6)]
Entry 2: [add x5, x3, x4]
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue: [sll x6, x1, #2]
Registers
x00: 0 2 3 -2 2 -4 4 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 51:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [lw x3, 312(x6)]
Entry 1: [lw x4, 324(x6)]
Entry 2: [add x5, x3, x4]
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -2 2 -4 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 52:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [lw x4, 324(x6)]
Entry 1: [add x5, x3, x4]
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0: [lw x3, 312(x6)]
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -2 2 -4 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 53:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [add x5, x3, x4]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0: [lw x4, 324(x6)]
Entry 1:
Pre-MEM Queue: [lw x3, 312(x6)]
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -2 2 -4 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 54:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [add x5, x3, x4]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue: [lw x4, 324(x6)]
Post-MEM Queue: [lw x3, 312(x6)]
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -2 2 -4 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 55:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [add x5, x3, x4]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue: [lw x4, 324(x6)]
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -4 2 -4 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 56:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0: [add x5, x3, x4]
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -4 3 -4 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 57:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue: [add x5, x3, x4]
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -4 3 -4 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 58:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue: [add x5, x3, x4]
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -4 3 -4 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 59:
IF Unit:
Waiting: [blt x5, x0, #6]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -4 3 -1 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 60:
IF Unit:
Waiting:
Executed: [blt x5, x0, #6]
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -4 3 -1 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 61:
IF Unit:
Waiting:
Executed:
Pre-Issue Queue:
Entry 0: [sw x5, 324(x6)]
Entry 1: [addi x1, x1, #1]
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -4 3 -1 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 62:
IF Unit:
Waiting:
Executed: [jal x8, #-20]
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0: [sw x5, 324(x6)]
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue: [addi x1, x1, #1]
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -4 3 -1 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 63:
IF Unit:
Waiting: [beq x1, x2, #22]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue: [sw x5, 324(x6)]
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue: [addi x1, x1, #1]
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 2 3 -4 3 -1 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 3 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 64:
IF Unit:
Waiting: [beq x1, x2, #22]
Executed:
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 3 3 -4 3 -1 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 -1 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 65:
IF Unit:
Waiting:
Executed: [beq x1, x2, #22]
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 3 3 -4 3 -1 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 -1 -4 10
344: 7 9 1 0 -1
--------------------
Cycle 66:
IF Unit:
Waiting:
Executed: [break]
Pre-Issue Queue:
Entry 0:
Entry 1:
Entry 2:
Entry 3:
Pre-ALU1 Queue:
Entry 0:
Entry 1:
Pre-MEM Queue:
Post-MEM Queue:
Pre-ALU2 Queue:
Post-ALU2 Queue:
Pre-ALU3 Queue:
Post-ALU3 Queue:
Registers
x00: 0 3 3 -4 3 -1 8 296
x08: 308 0 0 0 0 0 0 0
x16: 0 0 0 0 0 0 0 0
x24: 0 0 0 0 0 0 0 0
Data
312: -1 -2 -4 1 2 -1 -4 10
344: 7 9 1 0 -1