Untitled

module main(
	A0,A1,A2,A3,B0,B1,B2,B3,CLK,
	pin_name9,pin_name10,pin_name11,pin_name12
);


input wire	A0,A1,A2,A3;
input wire	B0,B1,B2,B3;
input wire	CLK;
output wire	pin_name9,pin_name10,pin_name11,pin_name12;

wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;
wire	SYNTHESIZED_WIRE_3;
wire	SYNTHESIZED_WIRE_4;
wire	SYNTHESIZED_WIRE_5;
wire	SYNTHESIZED_WIRE_6;
wire	SYNTHESIZED_WIRE_7;
wire	SYNTHESIZED_WIRE_8;
wire	SYNTHESIZED_WIRE_9;
wire	SYNTHESIZED_WIRE_10;
wire	SYNTHESIZED_WIRE_11;



REG4	b2v_inst(
	.A0(A0),
	.A1(A1),
	.A2(A2),
	.A3(A3),
	.CLK(CLK),
	.Q1(SYNTHESIZED_WIRE_1),
	.Q2(SYNTHESIZED_WIRE_3),
	.Q3(SYNTHESIZED_WIRE_2),
	.Q4(SYNTHESIZED_WIRE_4));


REG4	b2v_inst1(
	.A0(B0),
	.A1(B1),
	.A2(B2),
	.A3(B3),
	.CLK(CLK),
	.Q1(SYNTHESIZED_WIRE_5),
	.Q2(SYNTHESIZED_WIRE_6),
	.Q3(SYNTHESIZED_WIRE_7),
	.Q4(SYNTHESIZED_WIRE_0));


\7483 	b2v_inst2(
	.B4(SYNTHESIZED_WIRE_0),
	
	.A1(SYNTHESIZED_WIRE_1),
	.A2(SYNTHESIZED_WIRE_2),
	.B1(SYNTHESIZED_WIRE_3),
	.B2(SYNTHESIZED_WIRE_4),
	.A3(SYNTHESIZED_WIRE_5),
	.B3(SYNTHESIZED_WIRE_6),
	.A4(SYNTHESIZED_WIRE_7),
	.S3(SYNTHESIZED_WIRE_10),
	.S4(SYNTHESIZED_WIRE_11),
	.S2(SYNTHESIZED_WIRE_9),
	
	.S1(SYNTHESIZED_WIRE_8));


REG4	b2v_inst3(
	.A0(SYNTHESIZED_WIRE_8),
	.A1(SYNTHESIZED_WIRE_9),
	.A2(SYNTHESIZED_WIRE_10),
	.A3(SYNTHESIZED_WIRE_11),
	.CLK(CLK),
	.Q1(pin_name9),
	.Q2(pin_name10),
	.Q3(pin_name11),
	.Q4(pin_name12));


endmodule