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#define AM_HAL_IOM_INT_CQERR IOM0_INTEN_CQERR_Msk //! Error during command queue operations #define AM_HAL_IOM_INT_CQUPD IOM0_INTEN_CQUPD_Msk //! Command queue operation performed a register write with the register address bit 0 set to 1. #define AM_HAL_IOM_INT_CQPAUSED IOM0_INTEN_CQPAUSED_Msk //! Command queue operation paused #define AM_HAL_IOM_INT_DERR IOM0_INTEN_DERR_Msk //! DMA error received #define AM_HAL_IOM_INT_DCMP IOM0_INTEN_DCMP_Msk //! DMA transfer complete #define AM_HAL_IOM_INT_ARB IOM0_INTEN_ARB_Msk //! Arbitration loss #define AM_HAL_IOM_INT_STOP IOM0_INTEN_STOP_Msk //! STOP command #define AM_HAL_IOM_INT_START IOM0_INTEN_START_Msk //! START command #define AM_HAL_IOM_INT_ICMD IOM0_INTEN_ICMD_Msk //! ILLEGAL command #define AM_HAL_IOM_INT_IACC IOM0_INTEN_IACC_Msk //! Illegal FIFO access #define AM_HAL_IOM_INT_NAK IOM0_INTEN_NAK_Msk //! I2C NAK #define AM_HAL_IOM_INT_FOVFL IOM0_INTEN_FOVFL_Msk //! Write FIFO overflow #define AM_HAL_IOM_INT_FUNDFL IOM0_INTEN_FUNDFL_Msk //! Read FIFO underflow #define AM_HAL_IOM_INT_THR IOM0_INTEN_THR_Msk //! FIFO threshold interrupt #define AM_HAL_IOM_INT_CMDCMP IOM0_INTEN_CMDCMP_Msk //! Command complete #define AM_HAL_IOM_INT_SWERR (AM_HAL_IOM_INT_ICMD | AM_HAL_IOM_INT_IACC | AM_HAL_IOM_INT_FOVFL | AM_HAL_IOM_INT_FUNDFL) #define AM_HAL_IOM_INT_I2CARBERR (AM_HAL_IOM_INT_ARB) #define AM_HAL_IOM_INT_INTERR (AM_HAL_IOM_INT_CQERR | AM_HAL_IOM_INT_DERR) #define AM_HAL_IOM_INT_ALL 0xFFFFFFFF // //! Unsuccessful end of a transaction results in one more more of the following // #define AM_HAL_IOM_INT_ERR (AM_HAL_IOM_INT_SWERR | AM_HAL_IOM_INT_I2CARBERR | AM_HAL_IOM_INT_INTERR | AM_HAL_IOM_INT_NAK)
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