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#include "dmauart.h"

#define DMA2EN (1U<<22)
#define DMA_SCR	(1U<<0)
#define DMA_SCR_MINC (1U<<10)
#define DMA_SCR_PINC (1U<<9)
#define DMA_SCR_TCIE (1U<<4)
#define DMA_SCR_TEIE (1U<<2)
#define DMA_SCR_DMEIE (1U<<1)
#define DMA_SCFR_DMDIS (1U<<2)


void dma2_mem2mem_config(void){
	//enable clock accces to dma module
	RCC->AHB1ENR |= DMA2EN;
	//disable dma stream
	DMA2_Stream0->CR = 0;
	//wait until stream is disabled
	while(DMA2_Stream0->CR & DMA_SCR){}

	//configure dma parameters
	//set MSIZE to half word(16bit)
	DMA2_Stream0->CR |= (1U<<13);
	DMA2_Stream0->CR &= ~(1U<<14);
	//set PSIZE to half word(16bit)
	DMA2_Stream0->CR |= (1U<<11);
	DMA2_Stream0->CR &= ~(1U<<12);
	//enable memory increment
	DMA2_Stream0->CR |= DMA_SCR_MINC;
	//enable peripheral increment
	DMA2_Stream0->CR |= DMA_SCR_PINC;
	//select mem to mem transfer
	DMA2_Stream0->CR |= (1U<<7);
	DMA2_Stream0->CR &= ~(1U<<6);
	//enable transfer complete interrupt
	DMA2_Stream0->CR |= DMA_SCR_TCIE;
	//enable transfer error interrupt
	DMA2_Stream0->CR |= DMA_SCR_TEIE;
	//disable direct mode
	DMA2_Stream0->FCR |= DMA_SCFR_DMDIS;
	//set dma FIFO threshold
	DMA2_Stream0->FCR |= (1U<<0);
	DMA2_Stream0->FCR |= (1U<<1);
	//enable dma interrupt in NVIC
	NVIC_EnableIRQ(DMA2_Stream0_IRQn);
}

void dma_transfer_start(uint32_t src_buff,uint32_t des_buff,uint32_t len){
	//set peripheral address
	DMA2_Stream0->PAR = src_buff;
	//set memory address
	DMA2_Stream0->M0AR = des_buff;
	//set transfer length
	DMA2_Stream0->NDTR = len;
	//enable DMA stream
	DMA2_Stream0->CR |= DMA_SCR;
}
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