Untitled

`timescale 1ns / 1ps

module model_uart(/*AUTOARG*/
   // Outputs
   TX,
   // Inputs
   RX
   );

   output TX;
   input  RX;

   parameter baud    = 115200;
   parameter bittime = 1000000000/baud;
   parameter name    = "UART0";
   
   reg [7:0] rxData;
   event     evBit;
   event     evByte;
   event     evTxBit;
   event     evTxByte;
   reg       TX;
   
   reg [7:0] rxBuffer [0:3];  
   integer   byteCount = 0;
   
   initial
     begin
        TX = 1'b1;
     end
   /*
   always @ (negedge RX)
     begin
        rxData[7:0] = 8'h0;
        #(0.5*bittime);
        repeat (8)
          begin
             #bittime ->evBit;
             //rxData[7:0] = {rxData[6:0],RX};
             rxData[7:0] = {RX,rxData[7:1]};
          end
        ->evByte;
        $display ("%d %s Received byte %02x (%s)", $stime, name, rxData, rxData);
     end*/
     
    always @ (negedge RX)
         begin
            rxData[7:0] = 8'h0;
            #(0.5*bittime);
            repeat (8)
              begin
                 #bittime ->evBit;
                 rxData[7:0] = {RX,rxData[7:1]};
              end
              
//            rxBuffer[byteCount] = rxData;
//            byteCount = byteCount + 1;
            
            if (rxData != 8'h0A && rxData != 8'h72) begin
                rxBuffer[byteCount] = rxData;
                byteCount = byteCount + 1;
            end
            
            if (byteCount == 4) begin
               $display ("%d %s Received bytes %s", 
                         $stime, name, 
                         {rxBuffer[0], rxBuffer[1], rxBuffer[2], rxBuffer[3]});
               byteCount = 0;
            end
            ->evByte;
         end

   task tskRxData;
      output [7:0] data;
      begin
         @(evByte);
         data = rxData;
      end
   endtask // for
      
   task tskTxData;
      input [7:0] data;
      reg [9:0]   tmp;
      integer     i;
      begin
         tmp = {1'b1, data[7:0], 1'b0};
         for (i=0;i<10;i=i+1)
           begin
              TX = tmp[i];
              #bittime;
              ->evTxBit;
           end
         ->evTxByte;
      end
   endtask // tskTxData
   
endmodule // model_uart