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`include "global.v"
/*
`define BCD_BIT_WIDTH 4
`define DISABLE 1'b0
`define ENABLE 1'b1
*/

module counterx(
    output reg [`BCD_BIT_WIDTH - 1:0] value,
    output reg carry,
    input count_en,
    input [`BCD_BIT_WIDTH - 1:0] init_value,
    input [`BCD_BIT_WIDTH - 1:0] lmt_value,
    input [`BCD_BIT_WIDTH - 1:0] rst_value,
    input clk,
    input rst_n
);

    reg [`BCD_BIT_WIDTH - 1:0] value_tmp;

    // combanational
    always @* begin
        if (value == lmt_value && count_en) begin
            carry = `ENABLE;
            value_tmp = init_value;
        end else if (count_en) begin
            carry = `DISABLE;
            value_tmp = value + 1'b1;
        end else begin
            carry = `DISABLE;
            value_tmp = value;
        end
    end

    // sequential
    always @(posedge clk or negedge rst_n) begin
        if (~rst_n)
            value <= rst_value;
        else 
            value <= value_tmp;
    end

endmodule