Untitled

-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;

entity f_a is
port (x, y, cin: in bit;
      sum, cout: out bit);
      end f_a;

      architecture structure of f_a is
      component and2
      port(X1, X2: in bit; O: out bit);
      end component;

      component xor2
      port(X1, X2: in bit; O: out bit);
      end component;

      component or3
      port(X1,X2,X3: in bit; O: out bit);
      end component;

      signal s0,s1,s2, s3:bit;
      begin
      u0: xor2 port map (x,y, s0);
      u1: xor2 port map (s0, cin, sum);
      u2: and2 port map (x,y,s1);
      u3: and2 port map (x,cin,s2);
      u4: and2 port map (y,cin, s3);
      u5: or3 port map (s1,s2,s3, cout);
      end structure;

      entity and2 is port (
        X1, X2: in bit; O: out bit);
        end and2;

        architecture behave of and2 is
        begin
        
      )