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## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] ## Input switches for i_add1 set_property PACKAGE_PIN V17 [get_ports {i_add1[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_add1[0]}] set_property PACKAGE_PIN V16 [get_ports {i_add1[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_add1[1]}] set_property PACKAGE_PIN W16 [get_ports {i_add1[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_add1[2]}] set_property PACKAGE_PIN W17 [get_ports {i_add1[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_add1[3]}] ## Input switches for i_add2 set_property PACKAGE_PIN W15 [get_ports {i_add2[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_add2[0]}] set_property PACKAGE_PIN V15 [get_ports {i_add2[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_add2[1]}] set_property PACKAGE_PIN W14 [get_ports {i_add2[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_add2[2]}] set_property PACKAGE_PIN V14 [get_ports {i_add2[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_add2[3]}] ## Output LEDs for o_result set_property PACKAGE_PIN U16 [get_ports {o_result[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {o_result[0]}] set_property PACKAGE_PIN E19 [get_ports {o_result[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {o_result[1]}] set_property PACKAGE_PIN U19 [get_ports {o_result[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {o_result[2]}] set_property PACKAGE_PIN V19 [get_ports {o_result[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {o_result[3]}] set_property PACKAGE_PIN W18 [get_ports {o_result[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {o_result[4]}] module top ( input clk, input [3:0] i_add1, input [3:0] i_add2, output [4:0] o_result ); // Instantiate the pipelined adder pipelined_carry_lookahead_adder #(4) uut ( .clk(clk), .i_add1(i_add1), .i_add2(i_add2), .o_result(o_result) ); endmodule
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