Untitled
unknown
plain_text
a year ago
581 kB
3
Indexable
PrimeTime (R)
PrimeTime (R) SI
Version V-2003.12-1 for sparcOS5 -- Dec 17, 2003
Copyright (c) 1988-2003 by Synopsys, Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys, Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Initializing gui preferences from file /remote/training/home/anjalika/.synopsys_pt_prefs.tcl
set link_path "core_slow.db io_slow.db CLKMUL_lib.db PLL_lib.db *"
core_slow.db io_slow.db CLKMUL_lib.db PLL_lib.db *
read_verilog orca.v
Loading verilog file '/remote/training/home/anjalika/power_Tcl/design_data/orca.v'
1
link_design ORCA
Loading db file '/remote/training/home/anjalika/power_Tcl/libs/core_slow.db'
Loading db file '/remote/training/home/anjalika/power_Tcl/libs/io_slow.db'
Loading db file '/remote/training/home/anjalika/power_Tcl/design_data/CLKMUL_lib.db'
Loading db file '/remote/training/home/anjalika/power_Tcl/design_data/PLL_lib.db'
Linking design ORCA...
Designs used to link ORCA:
ALU, BLENDER, CLOCK_GEN, CONTROL, DATA_PATH, INSTRN_LAT, ORCA_TOP,
PARSER, PCI_CORE, PCI_RFIFO, PCI_WFIFO, PCI_W_MUX, PRGRM_CNT_TOP,
REG_FILE, RESET_BLOCK, RISC_CORE, SDRAM_IF, SDRAM_RFIFO,
SDRAM_WFIFO, SD_W_MUX, STACK_TOP
Libraries used to link ORCA:
CLKMUL_lib, PLL_lib, core_slow.db, io_slow.db
Design 'ORCA' was successfully linked.
1
source orca_const_func.tcl
# Functional mode analysis
set_case_analysis 0 [get_ports "test_mode scan_en"]
1
set_case_analysis 0 [get_ports power_save]
1
set_case_analysis 1 [get_ports pm66en]
1
report_timing -max 10
Information: Using automatic max wire load selection group 'AreaBasedWireLoadSelection'. (ENV-003)
Warning: Some timing arcs have been disabled for breaking timing loops
or because of constant propagation. Use the 'report_disable_timing'
command to get the list of these disabled timing arcs. (PTE-003)
Information: Inferring 65 clock-gating checks. (PTE-017)
Information: Inferring 65 clock-gating checks. (PTE-017)
Information: Zero transition time used at to pin of annotated arcs. Delays on not annotated delay arcs will be estimated using best available slew. (PTE-054)
Information: Expanding clock 'SYS_2x_CLK' to base period of 10.00
(old period was 5.00, added 2 edges). (PTE-016)
****************************************
Report : timing
-path full
-delay max
-max_paths 10
Design : ORCA
Version: V-2003.12-1
Date : Fri Jan 23 08:48:57 2004
****************************************
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/STACK_FULL_reg
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32206/Y (clk1a27) 0.32 4.54 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32212/Y (clk1a27) 0.29 4.83 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32299/Y (clk1a27) 0.32 5.15 r
I_ORCA_TOP/I_RISC_CORE/reset_nbq (RISC_CORE) 0.00 5.15 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/reset_ne (STACK_TOP)
0.00 5.15 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U99/Y (inv1a1) 0.08 5.23 f
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U181/Y (inv1a1) 0.21 5.44 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/STACK_FULL_reg/CLR (fdmf2a15)
0.00 5.44 r
data arrival time 5.44
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.56 7.56
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/STACK_FULL_reg/CLK (fdmf2a15)
7.56 r
library recovery time 0.00 7.56
data required time 7.56
------------------------------------------------------------------------------
data required time 7.56
data arrival time -5.44
------------------------------------------------------------------------------
slack (MET) 2.12
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][7]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32206/Y (clk1a27) 0.32 4.54 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32269/Y (clk1a27) 0.29 4.83 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32350/Y (buf1a6) 0.11 4.94 r
I_ORCA_TOP/CTS_sys_2x_rst_L5I32351/Y (buf1a6) 0.11 5.05 r
I_ORCA_TOP/I_RISC_CORE/reset_nci (RISC_CORE) 0.00 5.05 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nbk (REG_FILE)
0.00 5.05 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U136/Y (inv1a1) 0.07 5.11 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U445/Y (inv1a1) 0.28 5.39 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][7]/CLR (fdesf2a3)
0.00 5.39 r
data arrival time 5.39
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.56 7.56
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][7]/CLK (fdesf2a3)
7.56 r
library recovery time 0.00 7.56
data required time 7.56
------------------------------------------------------------------------------
data required time 7.56
data arrival time -5.39
------------------------------------------------------------------------------
slack (MET) 2.17
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/TOS_int_reg[1]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32204/Y (clk1a27) 0.34 4.56 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32294/Y (clk1a27) 0.30 4.86 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32375/Y (buf1a6) 0.23 5.09 r
I_ORCA_TOP/I_RISC_CORE/reset_nbk (RISC_CORE) 0.00 5.09 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/reset_nb (STACK_TOP)
0.00 5.09 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U102/Y (inv1a27) 0.04 5.13 f
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U179/Y (inv1a1) 0.24 5.36 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/TOS_int_reg[1]/CLR (fdmf2a3)
0.00 5.36 r
data arrival time 5.36
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.54 7.54
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/TOS_int_reg[1]/CLK (fdmf2a3)
7.54 r
library recovery time 0.00 7.54
data required time 7.54
------------------------------------------------------------------------------
data required time 7.54
data arrival time -5.36
------------------------------------------------------------------------------
slack (MET) 2.17
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][14]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32209/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32260/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32342/Y (clk1a6) 0.11 4.99 r
I_ORCA_TOP/I_RISC_CORE/reset_ncd (RISC_CORE) 0.00 4.99 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nbg (REG_FILE)
0.00 4.99 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U145/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U436/Y (inv1a1) 0.28 5.33 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][14]/CLR (fdesf2a15)
0.00 5.33 r
data arrival time 5.33
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][14]/CLK (fdesf2a15)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.33
------------------------------------------------------------------------------
slack (MET) 2.18
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[0][10]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32209/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32288/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32369/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_ncb (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nbf (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U117/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U464/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[0][10]/CLR (fdesf2a3)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[0][10]/CLK (fdesf2a3)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][8]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32203/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32270/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32352/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_nbf (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nao (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U135/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U446/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][8]/CLR (fdesf2a15)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][8]/CLK (fdesf2a15)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][10]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32209/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32272/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32354/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_nbz (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nbd (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U133/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U448/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][10]/CLR (fdesf2a15)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][10]/CLK (fdesf2a15)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][10]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32209/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32256/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32338/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_nce (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nbh (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U149/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U432/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][10]/CLR (fdesf2a15)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][10]/CLK (fdesf2a15)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][13]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32203/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32259/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32341/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_nbd (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nam (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U146/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U435/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][13]/CLR (fdesf2a15)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][13]/CLK (fdesf2a15)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[3][14]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32209/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32244/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32329/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_nca (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nbe (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U161/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U420/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[3][14]/CLR (fdesf2a15)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[3][14]/CLK (fdesf2a15)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_0_reg[29]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1178
(falling clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.04 2.04
I_ORCA_TOP/I_SDRAM_IF/DQ_out_0_reg[29]/CLK (fdmf1a3)
0.00 2.04 r
I_ORCA_TOP/I_SDRAM_IF/DQ_out_0_reg[29]/Q (fdmf1a3) 0.74 2.78 f
I_ORCA_TOP/I_SDRAM_IF/U1178/D0 (mx2a15) 0.00 2.78 f
data arrival time 2.78
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.89 5.64
I_ORCA_TOP/I_SDRAM_IF/U1178/S (mx2a15) 5.64 f
clock gating setup time 0.00 5.64
data required time 5.64
------------------------------------------------------------------------------
data required time 5.64
data arrival time -2.78
------------------------------------------------------------------------------
slack (MET) 2.86
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_0_reg[0]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1199
(falling clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.04 2.04
I_ORCA_TOP/I_SDRAM_IF/DQ_out_0_reg[0]/CLK (fdmf1a3) 0.00 2.04 r
I_ORCA_TOP/I_SDRAM_IF/DQ_out_0_reg[0]/Q (fdmf1a3) 0.71 2.76 f
I_ORCA_TOP/I_SDRAM_IF/U1199/D0 (mx2a15) 0.00 2.76 f
data arrival time 2.76
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.89 5.64
I_ORCA_TOP/I_SDRAM_IF/U1199/S (mx2a15) 5.64 f
clock gating setup time 0.00 5.64
data required time 5.64
------------------------------------------------------------------------------
data required time 5.64
data arrival time -2.76
------------------------------------------------------------------------------
slack (MET) 2.88
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[12]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1196
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.51 5.26
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[12]/CLK (fdmf1b6)
0.00 5.26 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[12]/Q (fdmf1b6) 0.57 5.84 r
I_ORCA_TOP/I_SDRAM_IF/U1196/D1 (mx2a15) 0.00 5.84 r
data arrival time 5.84
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.45 8.95
I_ORCA_TOP/I_SDRAM_IF/U1196/S (mx2a15) 8.95 r
clock gating setup time 0.00 8.95
data required time 8.95
------------------------------------------------------------------------------
data required time 8.95
data arrival time -5.84
------------------------------------------------------------------------------
slack (MET) 3.11
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[27]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1180
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.53 5.28
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[27]/CLK (fdmf1b6)
0.00 5.28 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[27]/Q (fdmf1b6) 0.58 5.86 r
I_ORCA_TOP/I_SDRAM_IF/U1180/D1 (mx2a15) 0.00 5.86 r
data arrival time 5.86
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.49 8.99
I_ORCA_TOP/I_SDRAM_IF/U1180/S (mx2a15) 8.99 r
clock gating setup time 0.00 8.99
data required time 8.99
------------------------------------------------------------------------------
data required time 8.99
data arrival time -5.86
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[15]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1193
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.53 5.28
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[15]/CLK (fdmf1b6)
0.00 5.28 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[15]/Q (fdmf1b6) 0.58 5.86 r
I_ORCA_TOP/I_SDRAM_IF/U1193/D1 (mx2a15) 0.00 5.86 r
data arrival time 5.86
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.49 8.99
I_ORCA_TOP/I_SDRAM_IF/U1193/S (mx2a15) 8.99 r
clock gating setup time 0.00 8.99
data required time 8.99
------------------------------------------------------------------------------
data required time 8.99
data arrival time -5.86
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[25]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1182
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.55 5.30
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[25]/CLK (fdmf1b6)
0.00 5.30 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[25]/Q (fdmf1b6) 0.59 5.89 r
I_ORCA_TOP/I_SDRAM_IF/U1182/D1 (mx2a15) 0.00 5.89 r
data arrival time 5.89
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.52 9.02
I_ORCA_TOP/I_SDRAM_IF/U1182/S (mx2a15) 9.02 r
clock gating setup time 0.00 9.02
data required time 9.02
------------------------------------------------------------------------------
data required time 9.02
data arrival time -5.89
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[17]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1191
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.55 5.30
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[17]/CLK (fdmf1b6)
0.00 5.30 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[17]/Q (fdmf1b6) 0.59 5.89 r
I_ORCA_TOP/I_SDRAM_IF/U1191/D1 (mx2a15) 0.00 5.89 r
data arrival time 5.89
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.52 9.02
I_ORCA_TOP/I_SDRAM_IF/U1191/S (mx2a15) 9.02 r
clock gating setup time 0.00 9.02
data required time 9.02
------------------------------------------------------------------------------
data required time 9.02
data arrival time -5.89
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[21]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1186
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.56 5.31
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[21]/CLK (fdmf1b6)
0.00 5.31 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[21]/Q (fdmf1b6) 0.60 5.90 r
I_ORCA_TOP/I_SDRAM_IF/U1186/D1 (mx2a15) 0.00 5.90 r
data arrival time 5.90
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.53 9.03
I_ORCA_TOP/I_SDRAM_IF/U1186/S (mx2a15) 9.03 r
clock gating setup time 0.00 9.03
data required time 9.03
------------------------------------------------------------------------------
data required time 9.03
data arrival time -5.90
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[24]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1183
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.55 5.30
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[24]/CLK (fdmf1b6)
0.00 5.30 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[24]/Q (fdmf1b6) 0.59 5.88 r
I_ORCA_TOP/I_SDRAM_IF/U1183/D1 (mx2a15) 0.00 5.89 r
data arrival time 5.89
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.52 9.02
I_ORCA_TOP/I_SDRAM_IF/U1183/S (mx2a15) 9.02 r
clock gating setup time 0.00 9.02
data required time 9.02
------------------------------------------------------------------------------
data required time 9.02
data arrival time -5.89
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[11]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1197
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.55 5.30
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[11]/CLK (fdmf1b6)
0.00 5.30 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[11]/Q (fdmf1b6) 0.59 5.88 r
I_ORCA_TOP/I_SDRAM_IF/U1197/D1 (mx2a15) 0.00 5.89 r
data arrival time 5.89
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.52 9.02
I_ORCA_TOP/I_SDRAM_IF/U1197/S (mx2a15) 9.02 r
clock gating setup time 0.00 9.02
data required time 9.02
------------------------------------------------------------------------------
data required time 9.02
data arrival time -5.89
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[0]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[0] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.33 1.33
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[0]/CLK (fdmf2a15) 0.00 1.33 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[0]/Q (fdmf2a15) 0.69 2.03 r
I_ORCA_TOP/I_PCI_CORE/pad_en[0] (PCI_CORE) 0.00 2.03 r
I_ORCA_TOP/pad_en[0] (ORCA_TOP) 0.00 2.03 r
scan_in_or_0/Y (or2a6) 0.29 2.31 r
pad_iopad_0/PAD (PCI66DGZ) 3.74 H 6.05 f
pad[0] (inout) 0.00 + 6.05 f
data arrival time 6.05
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -6.05
------------------------------------------------------------------------------
slack (MET) 6.91
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[4]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[4] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.15 1.15
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[4]/CLK (fdmf2a15) 0.00 1.15 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[4]/Q (fdmf2a15) 0.68 1.83 r
I_ORCA_TOP/I_PCI_CORE/pad_en[4] (PCI_CORE) 0.00 1.83 r
I_ORCA_TOP/pad_en[4] (ORCA_TOP) 0.00 1.83 r
scan_in_or_4/Y (or2a6) 0.29 2.11 r
pad_iopad_4/PAD (PCI66DGZ) 3.74 H 5.85 f
pad[4] (inout) 0.00 + 5.85 f
data arrival time 5.85
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.85
------------------------------------------------------------------------------
slack (MET) 7.11
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[5]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[5] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.15 1.15
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[5]/CLK (fdmf2a15) 0.00 1.15 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[5]/Q (fdmf2a15) 0.68 1.83 r
I_ORCA_TOP/I_PCI_CORE/pad_en[5] (PCI_CORE) 0.00 1.83 r
I_ORCA_TOP/pad_en[5] (ORCA_TOP) 0.00 1.83 r
scan_in_or_5/Y (or2a6) 0.29 2.11 r
pad_iopad_5/PAD (PCI66DGZ) 3.74 H 5.85 f
pad[5] (inout) 0.00 + 5.85 f
data arrival time 5.85
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.85
------------------------------------------------------------------------------
slack (MET) 7.11
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[1]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[1] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.13 1.13
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[1]/CLK (fdmf2a15) 0.00 1.13 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[1]/Q (fdmf2a15) 0.67 1.80 r
I_ORCA_TOP/I_PCI_CORE/pad_en[1] (PCI_CORE) 0.00 1.80 r
I_ORCA_TOP/pad_en[1] (ORCA_TOP) 0.00 1.80 r
scan_in_or_1/Y (or2a6) 0.29 2.09 r
pad_iopad_1/PAD (PCI66DGZ) 3.74 H 5.83 f
pad[1] (inout) 0.00 + 5.83 f
data arrival time 5.83
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.83
------------------------------------------------------------------------------
slack (MET) 7.13
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[2]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[2] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.13 1.13
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[2]/CLK (fdmf2a15) 0.00 1.13 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[2]/Q (fdmf2a15) 0.67 1.80 r
I_ORCA_TOP/I_PCI_CORE/pad_en[2] (PCI_CORE) 0.00 1.80 r
I_ORCA_TOP/pad_en[2] (ORCA_TOP) 0.00 1.80 r
scan_in_or_2/Y (or2a6) 0.29 2.09 r
pad_iopad_2/PAD (PCI66DGZ) 3.74 H 5.83 f
pad[2] (inout) 0.00 + 5.83 f
data arrival time 5.83
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.83
------------------------------------------------------------------------------
slack (MET) 7.13
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[3]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[3] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.13 1.13
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[3]/CLK (fdmf2a15) 0.00 1.13 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[3]/Q (fdmf2a15) 0.67 1.80 r
I_ORCA_TOP/I_PCI_CORE/pad_en[3] (PCI_CORE) 0.00 1.80 r
I_ORCA_TOP/pad_en[3] (ORCA_TOP) 0.00 1.80 r
scan_in_or_3/Y (or2a6) 0.29 2.09 r
pad_iopad_3/PAD (PCI66DGZ) 3.74 H 5.83 f
pad[3] (inout) 0.00 + 5.83 f
data arrival time 5.83
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.83
------------------------------------------------------------------------------
slack (MET) 7.13
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[9]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[9] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.33 1.33
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[9]/CLK (fdmf2a15) 0.00 1.33 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[9]/Q (fdmf2a15) 0.75 2.09 r
I_ORCA_TOP/I_PCI_CORE/pad_en[9] (PCI_CORE) 0.00 2.09 r
I_ORCA_TOP/pad_en[9] (ORCA_TOP) 0.00 2.09 r
pad_iopad_9/PAD (PCI66DGZ) 3.71 H 5.80 f
pad[9] (inout) 0.00 + 5.80 f
data arrival time 5.80
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.80
------------------------------------------------------------------------------
slack (MET) 7.16
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[24]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[24] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.33 1.33
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[24]/CLK (fdmf2a15) 0.00 1.33 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[24]/Q (fdmf2a15) 0.75 2.09 r
I_ORCA_TOP/I_PCI_CORE/pad_en[24] (PCI_CORE) 0.00 2.09 r
I_ORCA_TOP/pad_en[24] (ORCA_TOP) 0.00 2.09 r
pad_iopad_24/PAD (PCI66DGZ) 3.71 H 5.80 f
pad[24] (inout) 0.00 + 5.80 f
data arrival time 5.80
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.80
------------------------------------------------------------------------------
slack (MET) 7.16
Startpoint: I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg[17]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pserr_n (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.33 1.33
I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg[17]/CLK (fdmf2a15)
0.00 1.33 r
I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg[17]/Q (fdmf2a15)
0.75 2.09 r
I_ORCA_TOP/I_PCI_CORE/pserr_n_en (PCI_CORE) 0.00 2.09 r
I_ORCA_TOP/pserr_n_en (ORCA_TOP) 0.00 2.09 r
pserr_n_iopad/PAD (PCI66DGZ) 3.71 H 5.80 f
pserr_n (inout) 0.00 + 5.80 f
data arrival time 5.80
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.80
------------------------------------------------------------------------------
slack (MET) 7.16
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[16]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[16] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.33 1.33
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[16]/CLK (fdmf2a15) 0.00 1.33 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[16]/Q (fdmf2a15) 0.74 2.08 r
I_ORCA_TOP/I_PCI_CORE/pad_en[16] (PCI_CORE) 0.00 2.08 r
I_ORCA_TOP/pad_en[16] (ORCA_TOP) 0.00 2.08 r
pad_iopad_16/PAD (PCI66DGZ) 3.71 H 5.79 f
pad[16] (inout) 0.00 + 5.79 f
data arrival time 5.79
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.79
------------------------------------------------------------------------------
slack (MET) 7.18
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U1261
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U440/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[7] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[7] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U207/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1058/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U1029/Y (mx2d15) 0.26 13.13 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1261/D0 (fdmf1a6) 0.00 13.13 r
data arrival time 13.13
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.26 16.26
I_ORCA_TOP/I_PCI_READ_FIFO/U1261/CLK (fdmf1a6) 16.26 r
library setup time -0.18 16.08
data required time 16.08
------------------------------------------------------------------------------
data required time 16.08
data arrival time -13.13
------------------------------------------------------------------------------
slack (MET) 2.94
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U1021
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U440/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[7] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[7] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U207/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1058/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U1008/Y (mx2d15) 0.26 13.13 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1021/D0 (fdmf1a6) 0.00 13.13 r
data arrival time 13.13
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.26 16.26
I_ORCA_TOP/I_PCI_READ_FIFO/U1021/CLK (fdmf1a6) 16.26 r
library setup time -0.18 16.08
data required time 16.08
------------------------------------------------------------------------------
data required time 16.08
data arrival time -13.13
------------------------------------------------------------------------------
slack (MET) 2.94
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U439
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U438/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[5] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[5] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U205/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1074/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U554/Y (mx2d1) 0.21 13.08 r
I_ORCA_TOP/I_PCI_READ_FIFO/U439/D0 (fdmf1a6) 0.00 13.08 r
data arrival time 13.08
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.24 16.24
I_ORCA_TOP/I_PCI_READ_FIFO/U439/CLK (fdmf1a6) 16.24 r
library setup time -0.21 16.03
data required time 16.03
------------------------------------------------------------------------------
data required time 16.03
data arrival time -13.08
------------------------------------------------------------------------------
slack (MET) 2.95
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U681
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U437/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[4] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[4] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U204/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1059/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U432/Y (mx2d1) 0.21 13.08 r
I_ORCA_TOP/I_PCI_READ_FIFO/U681/D0 (fdmf1a6) 0.00 13.08 r
data arrival time 13.08
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.26 16.26
I_ORCA_TOP/I_PCI_READ_FIFO/U681/CLK (fdmf1a6) 16.26 r
library setup time -0.21 16.05
data required time 16.05
------------------------------------------------------------------------------
data required time 16.05
data arrival time -13.08
------------------------------------------------------------------------------
slack (MET) 2.97
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U445
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U440/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[7] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[7] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U207/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1058/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U552/Y (mx2d1) 0.21 13.08 r
I_ORCA_TOP/I_PCI_READ_FIFO/U445/D0 (fdmf1a3) 0.00 13.08 r
data arrival time 13.08
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.26 16.26
I_ORCA_TOP/I_PCI_READ_FIFO/U445/CLK (fdmf1a3) 16.26 r
library setup time -0.21 16.05
data required time 16.05
------------------------------------------------------------------------------
data required time 16.05
data arrival time -13.08
------------------------------------------------------------------------------
slack (MET) 2.97
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U344
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U438/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[5] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[5] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U205/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1074/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U675/Y (mx2d2) 0.15 13.03 r
I_ORCA_TOP/I_PCI_READ_FIFO/U344/D0 (fdmf1a6) 0.00 13.03 r
data arrival time 13.03
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.24 16.24
I_ORCA_TOP/I_PCI_READ_FIFO/U344/CLK (fdmf1a6) 16.24 r
library setup time -0.20 16.04
data required time 16.04
------------------------------------------------------------------------------
data required time 16.04
data arrival time -13.03
------------------------------------------------------------------------------
slack (MET) 3.02
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U384
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U438/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[5] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[5] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U205/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1074/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U700/Y (mx2d2) 0.15 13.03 r
I_ORCA_TOP/I_PCI_READ_FIFO/U384/D0 (fdmf1a6) 0.00 13.03 r
data arrival time 13.03
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.24 16.24
I_ORCA_TOP/I_PCI_READ_FIFO/U384/CLK (fdmf1a6) 16.24 r
library setup time -0.20 16.04
data required time 16.04
------------------------------------------------------------------------------
data required time 16.04
data arrival time -13.03
------------------------------------------------------------------------------
slack (MET) 3.02
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U1310
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U440/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[7] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[7] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U207/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1058/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U730/Y (mx2d2) 0.15 13.03 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1310/D0 (fdmf1a6) 0.00 13.03 r
data arrival time 13.03
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.24 16.24
I_ORCA_TOP/I_PCI_READ_FIFO/U1310/CLK (fdmf1a6) 16.24 r
library setup time -0.20 16.04
data required time 16.04
------------------------------------------------------------------------------
data required time 16.04
data arrival time -13.03
------------------------------------------------------------------------------
slack (MET) 3.02
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U2331
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U437/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[4] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[4] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U204/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1059/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U615/Y (mx2d2) 0.15 13.03 r
I_ORCA_TOP/I_PCI_READ_FIFO/U2331/D0 (fdmf1a6) 0.00 13.03 r
data arrival time 13.03
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.24 16.24
I_ORCA_TOP/I_PCI_READ_FIFO/U2331/CLK (fdmf1a6) 16.24 r
library setup time -0.20 16.04
data required time 16.04
------------------------------------------------------------------------------
data required time 16.04
data arrival time -13.03
------------------------------------------------------------------------------
slack (MET) 3.02
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U4311
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U434/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[1] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[1] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U201/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1077/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U719/Y (mx2d2) 0.15 13.03 r
I_ORCA_TOP/I_PCI_READ_FIFO/U4311/D0 (fdmf1a6) 0.00 13.03 r
data arrival time 13.03
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.24 16.24
I_ORCA_TOP/I_PCI_READ_FIFO/U4311/CLK (fdmf1a6) 16.24 r
library setup time -0.20 16.04
data required time 16.04
------------------------------------------------------------------------------
data required time 16.04
data arrival time -13.03
------------------------------------------------------------------------------
slack (MET) 3.02
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U201
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[27]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U201/CLK (fdmf2a15) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U201/Q (fdmf2a15) 0.75 2.22 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1282/Y (inv1a9) 0.26 2.48 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1272/Y (or2c2) 0.29 2.77 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1602/Y (buf1a9) 0.37 3.14 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6710/Y (and2c1) 0.13 3.27 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6610/Y (and2c1) 0.54 3.81 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1642/Y (or3d2) 0.25 4.06 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[27] (SDRAM_WFIFO)
0.00 4.06 f
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[27] (SDRAM_IF) 0.00 4.06 f
I_ORCA_TOP/I_SDRAM_IF/U1314/Y (clk1b2) 0.20 4.26 r
I_ORCA_TOP/I_SDRAM_IF/U1315/Y (inv1a6) 0.07 4.32 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[27]/D0 (fdmf1b6) 0.00 4.32 f
data arrival time 4.32
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.53 5.28
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[27]/CLK (fdmf1b6) 5.28 f
library setup time -0.24 5.03
data required time 5.03
------------------------------------------------------------------------------
data required time 5.03
data arrival time -4.32
------------------------------------------------------------------------------
slack (MET) 0.71
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[15]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/CLK (fdmf2a6) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/Q (fdmf2a6) 0.65 2.12 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3891/Y (clk1b3) 0.15 2.27 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3921/Y (and2a6) 0.27 2.54 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U846/Y (and2a9) 0.26 2.81 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U271/Y (clk1a27) 0.37 3.17 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2312/Y (or2c3) 0.20 3.37 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6461/Y (or2c15) 0.13 3.50 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6471/Y (and3d15) 0.05 3.56 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2082/Y (or3d1) 0.22 3.77 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U146/Y (inv1a1) 0.11 3.88 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U145/Y (inv1a1) 0.41 4.30 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[15] (SDRAM_WFIFO)
0.00 4.30 r
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[15] (SDRAM_IF) 0.00 4.30 r
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[15]/D0 (fdmf1b6) 0.00 4.30 r
data arrival time 4.30
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.53 5.28
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[15]/CLK (fdmf1b6) 5.28 f
library setup time -0.23 5.05
data required time 5.05
------------------------------------------------------------------------------
data required time 5.05
data arrival time -4.30
------------------------------------------------------------------------------
slack (MET) 0.75
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[13]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/CLK (fdmf2a6) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/Q (fdmf2a6) 0.65 2.12 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3891/Y (clk1b3) 0.14 2.26 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U269/Y (and2a9) 0.24 2.49 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U268/Y (and2a6) 0.23 2.72 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6841/Y (buf1a27) 0.20 2.92 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U85/Y (or2c2) 0.28 3.20 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6541/Y (or2c15) 0.11 3.31 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6551/Y (and3d15) 0.13 3.43 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2062/Y (or3d1) 0.23 3.66 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U142/Y (inv1a1) 0.28 3.94 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1411/Y (inv1a3) 0.14 4.08 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[13] (SDRAM_WFIFO)
0.00 4.08 f
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[13] (SDRAM_IF) 0.00 4.08 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[13]/D0 (fdmf1b6) 0.00 4.08 f
data arrival time 4.08
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.56 5.31
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[13]/CLK (fdmf1b6) 5.31 f
library setup time -0.25 5.06
data required time 5.06
------------------------------------------------------------------------------
data required time 5.06
data arrival time -4.08
------------------------------------------------------------------------------
slack (MET) 0.98
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[26]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/CLK (fdmf2a6) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/Q (fdmf2a6) 0.65 2.12 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3891/Y (clk1b3) 0.14 2.26 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U269/Y (and2a9) 0.24 2.49 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U268/Y (and2a6) 0.23 2.72 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6841/Y (buf1a27) 0.20 2.92 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U5610/Y (or2c1) 0.19 3.11 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U5410/Y (or2c1) 0.30 3.41 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1532/Y (and3d6) 0.27 3.68 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U4381/Y (or3d6) 0.15 3.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[26] (SDRAM_WFIFO)
0.00 3.83 f
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[26] (SDRAM_IF) 0.00 3.83 f
I_ORCA_TOP/I_SDRAM_IF/U1300/Y (buf1a27) 0.18 4.00 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[26]/D0 (fdmf1b6) 0.00 4.00 f
data arrival time 4.00
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.50 5.25
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[26]/CLK (fdmf1b6) 5.25 f
library setup time -0.25 5.00
data required time 5.00
------------------------------------------------------------------------------
data required time 5.00
data arrival time -4.00
------------------------------------------------------------------------------
slack (MET) 1.00
Startpoint: I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/out_control_reg[27]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.61 1.61
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/CLK (fdmf1a3)
0.00 1.61 r
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/Q (fdmf1a3)
0.65 2.26 r
I_ORCA_TOP/I_SDRAM_IF/U707/Y (clk1b3) 0.22 2.48 f
I_ORCA_TOP/I_SDRAM_IF/U1133/Y (or3a15) 0.40 2.88 f
I_ORCA_TOP/I_SDRAM_IF/U1216/Y (inv1a27) 0.06 2.94 r
I_ORCA_TOP/I_SDRAM_IF/U1134/Y (or3c15) 0.28 3.22 f
I_ORCA_TOP/I_SDRAM_IF/U691/Y (clk1b3) 0.13 3.35 r
I_ORCA_TOP/I_SDRAM_IF/U664/Y (or3c3) 0.59 3.94 f
I_ORCA_TOP/I_SDRAM_IF/U1217/Y (inv1a27) 0.11 4.05 r
I_ORCA_TOP/I_SDRAM_IF/U684/Y (or2c9) 0.23 4.28 f
I_ORCA_TOP/I_SDRAM_IF/U1122/Y (or2c15) 0.15 4.42 r
I_ORCA_TOP/I_SDRAM_IF/U670/Y (or2a6) 0.32 4.74 r
I_ORCA_TOP/I_SDRAM_IF/U1114/Y (or2a15) 0.24 4.98 r
I_ORCA_TOP/I_SDRAM_IF/U1226/Y (or2a15) 0.20 5.18 r
I_ORCA_TOP/I_SDRAM_IF/U1111/Y (and2a1) 0.37 5.55 r
I_ORCA_TOP/I_SDRAM_IF/IU504/Y (or2c2) 0.27 5.82 f
I_ORCA_TOP/I_SDRAM_IF/IU546/Y (ao1f2) 0.36 6.18 r
I_ORCA_TOP/I_SDRAM_IF/IU548/Y (oa1f6) 0.11 6.29 f
I_ORCA_TOP/I_SDRAM_IF/U45/Y (and2c2) 0.29 6.58 r
I_ORCA_TOP/I_SDRAM_IF/U30/Y (oa1f6) 0.18 6.76 f
I_ORCA_TOP/I_SDRAM_IF/U1232/Y (clk1b6) 0.12 6.88 r
I_ORCA_TOP/I_SDRAM_IF/U1233/Y (or2c2) 0.19 7.07 f
I_ORCA_TOP/I_SDRAM_IF/U1229/Y (ao1f3) 0.27 7.34 r
I_ORCA_TOP/I_SDRAM_IF/IU858/Y (xor2b2) 0.23 7.57 r
I_ORCA_TOP/I_SDRAM_IF/U748/Y (ao4e9) 0.39 7.95 r
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[27]/D0 (fdmf2a6)
0.00 7.95 r
data arrival time 7.95
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.63 9.13
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[27]/CLK (fdmf2a6) 9.13 r
library setup time -0.14 8.99
data required time 8.99
------------------------------------------------------------------------------
data required time 8.99
data arrival time -7.95
------------------------------------------------------------------------------
slack (MET) 1.03
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[1]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/CLK (fdmf2a6) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/Q (fdmf2a6) 0.65 2.12 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3891/Y (clk1b3) 0.14 2.26 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U269/Y (and2a9) 0.24 2.49 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U268/Y (and2a6) 0.23 2.72 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6851/Y (buf1a27) 0.20 2.93 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U257/Y (or2c2) 0.28 3.20 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6291/Y (or2c15) 0.07 3.28 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2313/Y (and3d2) 0.28 3.56 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2282/Y (or3d3) 0.23 3.79 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[1] (SDRAM_WFIFO)
0.00 3.79 f
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[1] (SDRAM_IF) 0.00 3.79 f
I_ORCA_TOP/I_SDRAM_IF/U1354/Y (buf1a27) 0.21 4.00 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[1]/D0 (fdmf1b6) 0.00 4.00 f
data arrival time 4.00
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.55 5.30
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[1]/CLK (fdmf1b6) 5.30 f
library setup time -0.23 5.07
data required time 5.07
------------------------------------------------------------------------------
data required time 5.07
data arrival time -4.00
------------------------------------------------------------------------------
slack (MET) 1.07
Startpoint: I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/out_control_reg[25]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.61 1.61
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/CLK (fdmf1a3)
0.00 1.61 r
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/Q (fdmf1a3)
0.65 2.26 r
I_ORCA_TOP/I_SDRAM_IF/U707/Y (clk1b3) 0.22 2.48 f
I_ORCA_TOP/I_SDRAM_IF/U1133/Y (or3a15) 0.40 2.88 f
I_ORCA_TOP/I_SDRAM_IF/U1216/Y (inv1a27) 0.06 2.94 r
I_ORCA_TOP/I_SDRAM_IF/U1134/Y (or3c15) 0.28 3.22 f
I_ORCA_TOP/I_SDRAM_IF/U691/Y (clk1b3) 0.13 3.35 r
I_ORCA_TOP/I_SDRAM_IF/U664/Y (or3c3) 0.59 3.94 f
I_ORCA_TOP/I_SDRAM_IF/U1217/Y (inv1a27) 0.11 4.05 r
I_ORCA_TOP/I_SDRAM_IF/U684/Y (or2c9) 0.23 4.28 f
I_ORCA_TOP/I_SDRAM_IF/U1122/Y (or2c15) 0.15 4.42 r
I_ORCA_TOP/I_SDRAM_IF/U670/Y (or2a6) 0.32 4.74 r
I_ORCA_TOP/I_SDRAM_IF/U1114/Y (or2a15) 0.24 4.98 r
I_ORCA_TOP/I_SDRAM_IF/U1226/Y (or2a15) 0.20 5.18 r
I_ORCA_TOP/I_SDRAM_IF/U1111/Y (and2a1) 0.37 5.55 r
I_ORCA_TOP/I_SDRAM_IF/IU504/Y (or2c2) 0.27 5.82 f
I_ORCA_TOP/I_SDRAM_IF/IU546/Y (ao1f2) 0.36 6.18 r
I_ORCA_TOP/I_SDRAM_IF/IU548/Y (oa1f6) 0.11 6.29 f
I_ORCA_TOP/I_SDRAM_IF/U45/Y (and2c2) 0.29 6.58 r
I_ORCA_TOP/I_SDRAM_IF/U30/Y (oa1f6) 0.18 6.76 f
I_ORCA_TOP/I_SDRAM_IF/U1232/Y (clk1b6) 0.12 6.88 r
I_ORCA_TOP/I_SDRAM_IF/U1231/Y (or2c3) 0.14 7.02 f
I_ORCA_TOP/I_SDRAM_IF/U1230/Y (ao1f3) 0.26 7.28 r
I_ORCA_TOP/I_SDRAM_IF/IU799/Y (xor2b2) 0.23 7.51 r
I_ORCA_TOP/I_SDRAM_IF/U745/Y (ao4e9) 0.39 7.90 r
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[25]/D0 (fdmf2a6)
0.00 7.90 r
data arrival time 7.90
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.62 9.12
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[25]/CLK (fdmf2a6) 9.12 r
library setup time -0.14 8.97
data required time 8.97
------------------------------------------------------------------------------
data required time 8.97
data arrival time -7.90
------------------------------------------------------------------------------
slack (MET) 1.08
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[12]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/CLK (fdmf2a6) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/Q (fdmf2a6) 0.65 2.12 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3891/Y (clk1b3) 0.14 2.26 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3921/Y (and2a6) 0.23 2.49 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U846/Y (and2a9) 0.23 2.72 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U271/Y (clk1a27) 0.36 3.08 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U208/Y (or2c2) 0.28 3.35 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6581/Y (or2c15) 0.12 3.48 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6591/Y (and3d15) 0.15 3.63 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2052/Y (or3d6) 0.14 3.77 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[12] (SDRAM_WFIFO)
0.00 3.77 f
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[12] (SDRAM_IF) 0.00 3.77 f
I_ORCA_TOP/I_SDRAM_IF/U1320/Y (buf1a27) 0.17 3.94 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[12]/D0 (fdmf1b6) 0.00 3.94 f
data arrival time 3.94
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.51 5.26
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[12]/CLK (fdmf1b6) 5.26 f
library setup time -0.24 5.02
data required time 5.02
------------------------------------------------------------------------------
data required time 5.02
data arrival time -3.94
------------------------------------------------------------------------------
slack (MET) 1.08
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[6]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/CLK (fdmf2a6) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/Q (fdmf2a6) 0.65 2.12 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3891/Y (clk1b3) 0.14 2.26 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3921/Y (and2a6) 0.23 2.49 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U846/Y (and2a9) 0.23 2.72 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U271/Y (clk1a27) 0.36 3.08 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U244/Y (or2c3) 0.20 3.28 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U5871/Y (or2c15) 0.07 3.35 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2122/Y (and3d2) 0.28 3.63 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2092/Y (or3d3) 0.23 3.86 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[6] (SDRAM_WFIFO)
0.00 3.86 f
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[6] (SDRAM_IF) 0.00 3.86 f
I_ORCA_TOP/I_SDRAM_IF/U1362/Y (buf1a27) 0.21 4.07 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[6]/D0 (fdmf1b6) 0.00 4.07 f
data arrival time 4.07
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.63 5.38
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[6]/CLK (fdmf1b6) 5.38 f
library setup time -0.23 5.15
data required time 5.15
------------------------------------------------------------------------------
data required time 5.15
data arrival time -4.07
------------------------------------------------------------------------------
slack (MET) 1.08
Startpoint: I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/out_control_reg[30]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.61 1.61
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/CLK (fdmf1a3)
0.00 1.61 r
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/Q (fdmf1a3)
0.65 2.26 r
I_ORCA_TOP/I_SDRAM_IF/U707/Y (clk1b3) 0.22 2.48 f
I_ORCA_TOP/I_SDRAM_IF/U1133/Y (or3a15) 0.40 2.88 f
I_ORCA_TOP/I_SDRAM_IF/U1216/Y (inv1a27) 0.06 2.94 r
I_ORCA_TOP/I_SDRAM_IF/U1134/Y (or3c15) 0.28 3.22 f
I_ORCA_TOP/I_SDRAM_IF/U691/Y (clk1b3) 0.13 3.35 r
I_ORCA_TOP/I_SDRAM_IF/U664/Y (or3c3) 0.59 3.94 f
I_ORCA_TOP/I_SDRAM_IF/U1217/Y (inv1a27) 0.11 4.05 r
I_ORCA_TOP/I_SDRAM_IF/U684/Y (or2c9) 0.23 4.28 f
I_ORCA_TOP/I_SDRAM_IF/U1122/Y (or2c15) 0.15 4.42 r
I_ORCA_TOP/I_SDRAM_IF/U670/Y (or2a6) 0.32 4.74 r
I_ORCA_TOP/I_SDRAM_IF/U1114/Y (or2a15) 0.24 4.98 r
I_ORCA_TOP/I_SDRAM_IF/U1226/Y (or2a15) 0.20 5.18 r
I_ORCA_TOP/I_SDRAM_IF/U1111/Y (and2a1) 0.37 5.55 r
I_ORCA_TOP/I_SDRAM_IF/IU504/Y (or2c2) 0.27 5.82 f
I_ORCA_TOP/I_SDRAM_IF/IU546/Y (ao1f2) 0.36 6.18 r
I_ORCA_TOP/I_SDRAM_IF/IU548/Y (oa1f6) 0.11 6.29 f
I_ORCA_TOP/I_SDRAM_IF/U45/Y (and2c2) 0.29 6.58 r
I_ORCA_TOP/I_SDRAM_IF/U30/Y (oa1f6) 0.18 6.76 f
I_ORCA_TOP/I_SDRAM_IF/IU880/Y (ao1f6) 0.23 6.99 r
I_ORCA_TOP/I_SDRAM_IF/U52/Y (and2a1) 0.26 7.25 r
I_ORCA_TOP/I_SDRAM_IF/U51/Y (xor2a1) 0.22 7.47 r
I_ORCA_TOP/I_SDRAM_IF/U1126/Y (ao4e15) 0.41 7.88 r
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[30]/D0 (fdmf2a6)
0.00 7.88 r
data arrival time 7.88
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.61 9.11
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[30]/CLK (fdmf2a6) 9.11 r
library setup time -0.14 8.97
data required time 8.97
------------------------------------------------------------------------------
data required time 8.97
data arrival time -7.88
------------------------------------------------------------------------------
slack (MET) 1.09
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[0] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25560/Y (clk1a15) 0.16 1.16 r
I_ORCA_TOP/CTS_sd_L4I25581/Y (clk1a27) 0.88 2.04 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkm (SDRAM_IF) 0.00 2.04 r
I_ORCA_TOP/I_SDRAM_IF/U1199/Y (mx2a15) 0.51 2.56 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[0] (SDRAM_IF) 0.00 2.56 r
I_ORCA_TOP/sd_DQ_out[0] (ORCA_TOP) 0.00 2.56 r
sdram_DQ_iopad_0/PAD (PDD24DGZ) 2.22 H 4.78 r
sd_DQ[0] (inout) 0.00 + 4.78 r
data arrival time 4.78
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.78
------------------------------------------------------------------------------
slack (MET) 3.11
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[9] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25560/Y (clk1a15) 0.16 1.16 r
I_ORCA_TOP/CTS_sd_L4I25581/Y (clk1a27) 0.88 2.04 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkm (SDRAM_IF) 0.00 2.04 r
I_ORCA_TOP/I_SDRAM_IF/U1168/Y (mx2a15) 0.51 2.56 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[9] (SDRAM_IF) 0.00 2.56 r
I_ORCA_TOP/sd_DQ_out[9] (ORCA_TOP) 0.00 2.56 r
sdram_DQ_iopad_9/PAD (PDD24DGZ) 2.22 H 4.78 r
sd_DQ[9] (inout) 0.00 + 4.78 r
data arrival time 4.78
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.78
------------------------------------------------------------------------------
slack (MET) 3.11
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[29] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25560/Y (clk1a15) 0.16 1.16 r
I_ORCA_TOP/CTS_sd_L4I25581/Y (clk1a27) 0.88 2.04 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkm (SDRAM_IF) 0.00 2.04 r
I_ORCA_TOP/I_SDRAM_IF/U1178/Y (mx2a15) 0.51 2.56 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[29] (SDRAM_IF) 0.00 2.56 r
I_ORCA_TOP/sd_DQ_out[29] (ORCA_TOP) 0.00 2.56 r
sdram_DQ_iopad_29/PAD (PDD24DGZ) 2.22 H 4.78 r
sd_DQ[29] (inout) 0.00 + 4.78 r
data arrival time 4.78
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.78
------------------------------------------------------------------------------
slack (MET) 3.11
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[6] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25559/Y (clk1a15) 0.19 1.19 r
I_ORCA_TOP/CTS_sd_L4I25562/Y (clk1a27) 0.43 1.62 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkk (SDRAM_IF) 0.00 1.62 r
I_ORCA_TOP/I_SDRAM_IF/U1171/Y (mx2a15) 0.39 2.02 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[6] (SDRAM_IF) 0.00 2.02 r
I_ORCA_TOP/sd_DQ_out[6] (ORCA_TOP) 0.00 2.02 r
sdram_DQ_iopad_6/PAD (PDD24DGZ) 2.22 H 4.24 r
sd_DQ[6] (inout) 0.00 + 4.24 r
data arrival time 4.24
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.24
------------------------------------------------------------------------------
slack (MET) 3.66
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[7] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25557/Y (clk1a15) 0.17 1.17 r
I_ORCA_TOP/CTS_sd_L4I25561/Y (clk1a27) 0.42 1.59 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkd (SDRAM_IF) 0.00 1.59 r
I_ORCA_TOP/I_SDRAM_IF/U1170/Y (mx2a15) 0.39 1.99 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[7] (SDRAM_IF) 0.00 1.99 r
I_ORCA_TOP/sd_DQ_out[7] (ORCA_TOP) 0.00 1.99 r
sdram_DQ_iopad_7/PAD (PDD24DGZ) 2.22 H 4.21 r
sd_DQ[7] (inout) 0.00 + 4.21 r
data arrival time 4.21
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.21
------------------------------------------------------------------------------
slack (MET) 3.68
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[23] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25560/Y (clk1a15) 0.16 1.16 r
I_ORCA_TOP/CTS_sd_L4I25564/Y (clk1a27) 0.42 1.58 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clko (SDRAM_IF) 0.00 1.58 r
I_ORCA_TOP/I_SDRAM_IF/U1184/Y (mx2a15) 0.39 1.98 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[23] (SDRAM_IF) 0.00 1.98 r
I_ORCA_TOP/sd_DQ_out[23] (ORCA_TOP) 0.00 1.98 r
sdram_DQ_iopad_23/PAD (PDD24DGZ) 2.22 H 4.20 r
sd_DQ[23] (inout) 0.00 + 4.20 r
data arrival time 4.20
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.20
------------------------------------------------------------------------------
slack (MET) 3.69
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[30] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25560/Y (clk1a15) 0.16 1.16 r
I_ORCA_TOP/CTS_sd_L4I25564/Y (clk1a27) 0.42 1.58 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clko (SDRAM_IF) 0.00 1.58 r
I_ORCA_TOP/I_SDRAM_IF/U1176/Y (mx2a15) 0.39 1.98 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[30] (SDRAM_IF) 0.00 1.98 r
I_ORCA_TOP/sd_DQ_out[30] (ORCA_TOP) 0.00 1.98 r
sdram_DQ_iopad_30/PAD (PDD24DGZ) 2.22 H 4.20 r
sd_DQ[30] (inout) 0.00 + 4.20 r
data arrival time 4.20
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.20
------------------------------------------------------------------------------
slack (MET) 3.69
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[2] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25557/Y (clk1a15) 0.17 1.17 r
I_ORCA_TOP/CTS_sd_L4I25567/Y (clk1a27) 0.41 1.59 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkc (SDRAM_IF) 0.00 1.59 r
I_ORCA_TOP/I_SDRAM_IF/U1177/Y (mx2a15) 0.39 1.97 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[2] (SDRAM_IF) 0.00 1.97 r
I_ORCA_TOP/sd_DQ_out[2] (ORCA_TOP) 0.00 1.97 r
sdram_DQ_iopad_2/PAD (PDD24DGZ) 2.22 H 4.20 r
sd_DQ[2] (inout) 0.00 + 4.20 r
data arrival time 4.20
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.20
------------------------------------------------------------------------------
slack (MET) 3.70
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[8] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25560/Y (clk1a15) 0.16 1.16 r
I_ORCA_TOP/CTS_sd_L4I25565/Y (clk1a27) 0.42 1.58 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkp (SDRAM_IF) 0.00 1.58 r
I_ORCA_TOP/I_SDRAM_IF/U1169/Y (mx2a15) 0.39 1.97 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[8] (SDRAM_IF) 0.00 1.97 r
I_ORCA_TOP/sd_DQ_out[8] (ORCA_TOP) 0.00 1.97 r
sdram_DQ_iopad_8/PAD (PDD24DGZ) 2.22 H 4.19 r
sd_DQ[8] (inout) 0.00 + 4.19 r
data arrival time 4.19
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.19
------------------------------------------------------------------------------
slack (MET) 3.70
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[28] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25551/Y (clk1a15) 0.12 0.83 r
I_ORCA_TOP/CTS_sd_L2I25555/Y (clk1a15) 0.13 0.96 r
I_ORCA_TOP/CTS_sd_L3I25556/Y (clk1a15) 0.15 1.10 r
I_ORCA_TOP/CTS_sd_L4I25583/Y (clk1a27) 0.43 1.53 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkr (SDRAM_IF) 0.00 1.53 r
I_ORCA_TOP/I_SDRAM_IF/U1179/Y (mx2a15) 0.39 1.92 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[28] (SDRAM_IF) 0.00 1.92 r
I_ORCA_TOP/sd_DQ_out[28] (ORCA_TOP) 0.00 1.92 r
sdram_DQ_iopad_28/PAD (PDD24DGZ) 2.22 H 4.15 r
sd_DQ[28] (inout) 0.00 + 4.15 r
data arrival time 4.15
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.15
------------------------------------------------------------------------------
slack (MET) 3.75
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/TOS_int_reg[0]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/Neg_Flag (CONTROL) 0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/U106/Y (mx2d3) 0.19 4.64 f
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/U104/Y (xor2b2) 0.28 4.93 f
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/U103/Y (and2c6) 0.15 5.08 r
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/U139/Y (mx2d6) 0.21 5.29 f
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/U138/Y (and2c15) 0.32 5.61 r
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/PushEnbl (CONTROL) 0.00 5.61 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/PushEnbl (STACK_TOP)
0.00 5.61 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U119/Y (inv1a9) 0.27 5.88 f
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U1/Y (or2a15) 0.30 6.18 f
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/IU32/Y (or2c15) 0.06 6.24 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U51/Y (xor2b2) 0.33 6.57 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U166/Y (or3d15) 0.10 6.67 f
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U118/Y (and2a3) 0.16 6.83 f
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U117/Y (and2c3) 0.22 7.05 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/TOS_int_reg[0]/D0 (fdmf2a3)
0.00 7.05 r
data arrival time 7.05
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.54 7.54
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/TOS_int_reg[0]/CLK (fdmf2a3)
7.54 r
library setup time -0.20 7.34
data required time 7.34
------------------------------------------------------------------------------
data required time 7.34
data arrival time -7.05
------------------------------------------------------------------------------
slack (MET) 0.29
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Oprnd_A_reg[7]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_ALU/Zro_Flag_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Oprnd_A_reg[7]/CLK (fdmf1a9)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Oprnd_A_reg[7]/Q (fdmf1a9)
0.75 3.31 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Oprnd_A[7] (DATA_PATH)
0.00 3.31 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/Oprnd_A[7] (ALU) 0.00 3.31 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/I20/CO1 (facs3a3) 0.33 3.63 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/I21/CO1 (facsf1b3) 0.28 3.92 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/I22/CO1 (facsf2a3) 0.25 4.17 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/I23/CO1 (facsf1b3) 0.24 4.41 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/I24/CO1 (facsf2a3) 0.24 4.65 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/I26/Y (and2c2) 0.09 4.74 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/U705/Y (inv1a1) 0.17 4.91 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/U706/Y (clk1b2) 0.11 5.01 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/U2100/Y (ao1a9) 0.34 5.35 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/I34/S (facsf1b2) 0.36 5.71 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/U654/Y (buf1a27) 0.22 5.93 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/U430/Y (inv1a27) 0.05 5.98 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/U370/Y (and2c15) 0.06 6.04 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/U520/Y (and3d15) 0.19 6.23 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/U319/Y (or2c15) 0.16 6.39 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/U547/Y (and2c15) 0.13 6.52 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/U276/Y (or2c9) 0.11 6.63 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/U332/Y (and3d15) 0.17 6.79 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/Zro_Flag_reg/D0 (fdesf2a9)
0.00 6.79 r
data arrival time 6.79
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.54 7.54
I_ORCA_TOP/I_RISC_CORE/I_ALU/Zro_Flag_reg/CLK (fdesf2a9) 7.54 r
library setup time -0.39 7.15
data required time 7.15
------------------------------------------------------------------------------
data required time 7.15
data arrival time -6.79
------------------------------------------------------------------------------
slack (MET) 0.36
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[2]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U74/Y (oa4f2)
0.30 6.62 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U56/Y (ao1e3)
0.21 6.83 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[2]/D0 (fdesf2a9)
0.00 6.83 f
data arrival time 6.83
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[2]/CLK (fdesf2a9)
7.55 r
library setup time -0.32 7.24
data required time 7.24
------------------------------------------------------------------------------
data required time 7.24
data arrival time -6.83
------------------------------------------------------------------------------
slack (MET) 0.40
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[0]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U76/Y (oa4f2)
0.30 6.62 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U62/Y (ao1e3)
0.22 6.84 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[0]/D0 (fdesf2a6)
0.00 6.84 f
data arrival time 6.84
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.53 7.53
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[0]/CLK (fdesf2a6)
7.53 r
library setup time -0.28 7.25
data required time 7.25
------------------------------------------------------------------------------
data required time 7.25
data arrival time -6.84
------------------------------------------------------------------------------
slack (MET) 0.41
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[1]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U75/Y (oa4f2)
0.30 6.62 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U68/Y (ao1e3)
0.22 6.84 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[1]/D0 (fdesf2a6)
0.00 6.84 f
data arrival time 6.84
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[1]/CLK (fdesf2a6)
7.55 r
library setup time -0.28 7.27
data required time 7.27
------------------------------------------------------------------------------
data required time 7.27
data arrival time -6.84
------------------------------------------------------------------------------
slack (MET) 0.43
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[3]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U73/Y (oa4f2)
0.30 6.62 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U58/Y (ao1e3)
0.22 6.84 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[3]/D0 (fdesf2a6)
0.00 6.84 f
data arrival time 6.84
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[3]/CLK (fdesf2a6)
7.55 r
library setup time -0.28 7.27
data required time 7.27
------------------------------------------------------------------------------
data required time 7.27
data arrival time -6.84
------------------------------------------------------------------------------
slack (MET) 0.43
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[7]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U69/Y (oa4f2)
0.28 6.60 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U55/Y (ao1e3)
0.21 6.81 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[7]/D0 (fdesf2a9)
0.00 6.81 f
data arrival time 6.81
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.58 7.58
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[7]/CLK (fdesf2a9)
7.58 r
library setup time -0.32 7.26
data required time 7.26
------------------------------------------------------------------------------
data required time 7.26
data arrival time -6.81
------------------------------------------------------------------------------
slack (MET) 0.45
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[4]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U72/Y (oa4f2)
0.30 6.62 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U59/Y (ao1e3)
0.22 6.84 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[4]/D0 (fdesf2a6)
0.00 6.84 f
data arrival time 6.84
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.58 7.58
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[4]/CLK (fdesf2a6)
7.58 r
library setup time -0.28 7.30
data required time 7.30
------------------------------------------------------------------------------
data required time 7.30
data arrival time -6.84
------------------------------------------------------------------------------
slack (MET) 0.46
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[5]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U71/Y (oa4f2)
0.30 6.62 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U60/Y (ao1e3)
0.22 6.84 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[5]/D0 (fdesf2a6)
0.00 6.84 f
data arrival time 6.84
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.58 7.58
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[5]/CLK (fdesf2a6)
7.58 r
library setup time -0.28 7.30
data required time 7.30
------------------------------------------------------------------------------
data required time 7.30
data arrival time -6.84
------------------------------------------------------------------------------
slack (MET) 0.46
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[6]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U70/Y (oa4f2)
0.30 6.62 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U61/Y (ao1e3)
0.22 6.84 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[6]/D0 (fdesf2a6)
0.00 6.84 f
data arrival time 6.84
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.58 7.58
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[6]/CLK (fdesf2a6)
7.58 r
library setup time -0.28 7.30
data required time 7.30
------------------------------------------------------------------------------
data required time 7.30
data arrival time -6.84
------------------------------------------------------------------------------
slack (MET) 0.46
Startpoint: I_ORCA_TOP/I_BLENDER/s4_op2_reg[9]
(rising edge-triggered flip-flop clocked by SYS_CLK)
Endpoint: I_ORCA_TOP/I_BLENDER/s5_result_reg[31]
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.36 2.36
I_ORCA_TOP/I_BLENDER/s4_op2_reg[9]/CLK (fdmf1a3) 0.00 2.36 r
I_ORCA_TOP/I_BLENDER/s4_op2_reg[9]/Q (fdmf1a3) 0.57 2.92 f
I_ORCA_TOP/I_BLENDER/U91/Y (or2c1) 0.39 3.31 r
I_ORCA_TOP/I_BLENDER/U12/Y (ao1f2) 0.29 3.60 f
I_ORCA_TOP/I_BLENDER/U31/Y (oa1f3) 0.30 3.90 r
I_ORCA_TOP/I_BLENDER/IU677/Y (ao1f2) 0.15 4.05 f
I_ORCA_TOP/I_BLENDER/U17/Y (ao1a3) 0.25 4.30 f
I_ORCA_TOP/I_BLENDER/IU726/CO (fa1a1) 0.35 4.65 f
I_ORCA_TOP/I_BLENDER/IU769/CO (fa1a1) 0.38 5.03 f
I_ORCA_TOP/I_BLENDER/IU813/CO (fa1a3) 0.38 5.41 f
I_ORCA_TOP/I_BLENDER/IU852/CO (fa1a3) 0.36 5.77 f
I_ORCA_TOP/I_BLENDER/IU892/CO (fa1a3) 0.36 6.13 f
I_ORCA_TOP/I_BLENDER/IU927/CO (fa1a2) 0.36 6.49 f
I_ORCA_TOP/I_BLENDER/IU963/CO (fa1a3) 0.37 6.86 f
I_ORCA_TOP/I_BLENDER/IU994/CO (fa1a1) 0.36 7.22 f
I_ORCA_TOP/I_BLENDER/IU1026/CO (fa1a2) 0.38 7.60 f
I_ORCA_TOP/I_BLENDER/IU1053/CO (fa1a2) 0.37 7.96 f
I_ORCA_TOP/I_BLENDER/IU1081/CO (fa1a2) 0.37 8.33 f
I_ORCA_TOP/I_BLENDER/IU1104/CO (fa1a2) 0.37 8.71 f
I_ORCA_TOP/I_BLENDER/CU15151_IU1128/CO (fa1a3) 0.37 9.08 f
I_ORCA_TOP/I_BLENDER/CU15170_IU1147/CO (fa1a3) 0.36 9.44 f
I_ORCA_TOP/I_BLENDER/CU15190_IU1167/CO (fa1a3) 0.36 9.80 f
I_ORCA_TOP/I_BLENDER/CU15205_IU1182/CO (fa1a3) 0.36 10.16 f
I_ORCA_TOP/I_BLENDER/CU15221_IU1198/CO (fa1a3) 0.36 10.52 f
I_ORCA_TOP/I_BLENDER/CU15232_IU1209/CO (fa1a3) 0.36 10.89 f
I_ORCA_TOP/I_BLENDER/CU15244_IU1221/CO (fa1a3) 0.33 11.22 f
I_ORCA_TOP/I_BLENDER/U121/Y (xor3a1) 0.26 11.48 f
I_ORCA_TOP/I_BLENDER/s5_result_reg[31]/D0 (fdmf1a3) 0.00 11.48 f
data arrival time 11.48
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.38 12.38
I_ORCA_TOP/I_BLENDER/s5_result_reg[31]/CLK (fdmf1a3) 12.38 r
library setup time -0.31 12.07
data required time 12.07
------------------------------------------------------------------------------
data required time 12.07
data arrival time -11.48
------------------------------------------------------------------------------
slack (MET) 0.59
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1112
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U677/Y (mx2d1) 0.19 11.42 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1112/D0 (fdmf1a6) 0.00 11.42 f
data arrival time 11.42
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1112/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.42
------------------------------------------------------------------------------
slack (MET) 0.63
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1231
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U687/Y (mx2d1) 0.19 11.42 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1231/D0 (fdmf1a6) 0.00 11.42 f
data arrival time 11.42
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1231/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.42
------------------------------------------------------------------------------
slack (MET) 0.63
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1841
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U747/Y (mx2d1) 0.19 11.42 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1841/D0 (fdmf1a6) 0.00 11.42 f
data arrival time 11.42
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1841/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.42
------------------------------------------------------------------------------
slack (MET) 0.63
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2071
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U772/Y (mx2d2) 0.20 11.43 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2071/D0 (fdmf1a6) 0.00 11.43 f
data arrival time 11.43
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2071/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.06
data required time 12.06
------------------------------------------------------------------------------
data required time 12.06
data arrival time -11.43
------------------------------------------------------------------------------
slack (MET) 0.63
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U541
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U628/Y (mx2d1) 0.19 11.42 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U541/D0 (fdmf1a6) 0.00 11.42 f
data arrival time 11.42
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U541/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.42
------------------------------------------------------------------------------
slack (MET) 0.63
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1610
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U5911/Y (mx2d1) 0.19 11.42 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1610/D0 (fdmf1a6) 0.00 11.42 f
data arrival time 11.42
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1610/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.42
------------------------------------------------------------------------------
slack (MET) 0.63
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1721
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U737/Y (mx2d1) 0.19 11.42 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1721/D0 (fdmf1a6) 0.00 11.42 f
data arrival time 11.42
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1721/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.42
------------------------------------------------------------------------------
slack (MET) 0.63
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U961
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U662/Y (mx2d1) 0.19 11.42 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U961/D0 (fdmf1a3) 0.00 11.42 f
data arrival time 11.42
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U961/CLK (fdmf1a3) 12.36 r
library setup time -0.31 12.06
data required time 12.06
------------------------------------------------------------------------------
data required time 12.06
data arrival time -11.42
------------------------------------------------------------------------------
slack (MET) 0.64
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U612
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U195/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U240/Y (or2c3) 0.23 10.27 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U497/Y (inv1a9) 0.20 10.47 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U498/Y (inv1a27) 0.05 10.52 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[11] (REG_FILE)
0.00 10.52 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[11] (RISC_CORE) 0.00 10.52 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[27] (SD_W_MUX)
0.00 10.52 f
I_ORCA_TOP/I_SD_W_MUX/U74/Y (ao1e2) 0.19 10.71 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[27] (SD_W_MUX) 0.00 10.71 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[27] (SDRAM_WFIFO)
0.00 10.71 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U41/Y (clk1a3) 0.20 10.91 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2941/Y (clk1b6) 0.25 11.16 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U636/Y (mx2d2) 0.20 11.36 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U612/D0 (fdmf1a6) 0.00 11.36 f
data arrival time 11.36
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U612/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.36
------------------------------------------------------------------------------
slack (MET) 0.69
1
Information: Errors and/or warnings occurred at or before line 15 in
script '/remote/training/home/anjalika/power_Tcl/scripts/runtiming.tcl'. (CMD-082)
report_timing -max 15
****************************************
Report : timing
-path full
-delay max
-max_paths 15
Design : ORCA
Version: V-2003.12-1
Date : Fri Jan 23 08:48:58 2004
****************************************
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/STACK_FULL_reg
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32206/Y (clk1a27) 0.32 4.54 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32212/Y (clk1a27) 0.29 4.83 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32299/Y (clk1a27) 0.32 5.15 r
I_ORCA_TOP/I_RISC_CORE/reset_nbq (RISC_CORE) 0.00 5.15 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/reset_ne (STACK_TOP)
0.00 5.15 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U99/Y (inv1a1) 0.08 5.23 f
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U181/Y (inv1a1) 0.21 5.44 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/STACK_FULL_reg/CLR (fdmf2a15)
0.00 5.44 r
data arrival time 5.44
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.56 7.56
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/STACK_FULL_reg/CLK (fdmf2a15)
7.56 r
library recovery time 0.00 7.56
data required time 7.56
------------------------------------------------------------------------------
data required time 7.56
data arrival time -5.44
------------------------------------------------------------------------------
slack (MET) 2.12
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][7]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32206/Y (clk1a27) 0.32 4.54 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32269/Y (clk1a27) 0.29 4.83 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32350/Y (buf1a6) 0.11 4.94 r
I_ORCA_TOP/CTS_sys_2x_rst_L5I32351/Y (buf1a6) 0.11 5.05 r
I_ORCA_TOP/I_RISC_CORE/reset_nci (RISC_CORE) 0.00 5.05 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nbk (REG_FILE)
0.00 5.05 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U136/Y (inv1a1) 0.07 5.11 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U445/Y (inv1a1) 0.28 5.39 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][7]/CLR (fdesf2a3)
0.00 5.39 r
data arrival time 5.39
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.56 7.56
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][7]/CLK (fdesf2a3)
7.56 r
library recovery time 0.00 7.56
data required time 7.56
------------------------------------------------------------------------------
data required time 7.56
data arrival time -5.39
------------------------------------------------------------------------------
slack (MET) 2.17
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/TOS_int_reg[1]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32204/Y (clk1a27) 0.34 4.56 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32294/Y (clk1a27) 0.30 4.86 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32375/Y (buf1a6) 0.23 5.09 r
I_ORCA_TOP/I_RISC_CORE/reset_nbk (RISC_CORE) 0.00 5.09 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/reset_nb (STACK_TOP)
0.00 5.09 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U102/Y (inv1a27) 0.04 5.13 f
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U179/Y (inv1a1) 0.24 5.36 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/TOS_int_reg[1]/CLR (fdmf2a3)
0.00 5.36 r
data arrival time 5.36
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.54 7.54
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/TOS_int_reg[1]/CLK (fdmf2a3)
7.54 r
library recovery time 0.00 7.54
data required time 7.54
------------------------------------------------------------------------------
data required time 7.54
data arrival time -5.36
------------------------------------------------------------------------------
slack (MET) 2.17
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][14]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32209/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32260/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32342/Y (clk1a6) 0.11 4.99 r
I_ORCA_TOP/I_RISC_CORE/reset_ncd (RISC_CORE) 0.00 4.99 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nbg (REG_FILE)
0.00 4.99 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U145/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U436/Y (inv1a1) 0.28 5.33 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][14]/CLR (fdesf2a15)
0.00 5.33 r
data arrival time 5.33
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][14]/CLK (fdesf2a15)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.33
------------------------------------------------------------------------------
slack (MET) 2.18
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[0][10]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32209/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32288/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32369/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_ncb (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nbf (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U117/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U464/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[0][10]/CLR (fdesf2a3)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[0][10]/CLK (fdesf2a3)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][8]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32203/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32270/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32352/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_nbf (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nao (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U135/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U446/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][8]/CLR (fdesf2a15)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][8]/CLK (fdesf2a15)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][10]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32209/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32272/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32354/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_nbz (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nbd (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U133/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U448/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][10]/CLR (fdesf2a15)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][10]/CLK (fdesf2a15)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][12]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32209/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32274/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32355/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_ncg (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nbi (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U131/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U450/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][12]/CLR (fdesf2a15)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][12]/CLK (fdesf2a15)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][14]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32209/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32276/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32357/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_nby (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nbc (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U129/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U452/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][14]/CLR (fdesf2a15)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][14]/CLK (fdesf2a15)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][10]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32209/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32256/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32338/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_nce (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nbh (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U149/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U432/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][10]/CLR (fdesf2a15)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][10]/CLK (fdesf2a15)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][13]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32203/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32259/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32341/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_nbd (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nam (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U146/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U435/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][13]/CLR (fdesf2a15)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[2][13]/CLK (fdesf2a15)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[3][8]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32203/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32239/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32324/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_nbc (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nal (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U167/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U414/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[3][8]/CLR (fdesf2a3)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[3][8]/CLK (fdesf2a3)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[3][14]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32199/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32209/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32244/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32329/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_nca (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nbe (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U161/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U420/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[3][14]/CLR (fdesf2a15)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[3][14]/CLK (fdesf2a15)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][4]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32198/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32205/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32266/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32347/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_nad (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nq (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U139/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U442/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][4]/CLR (fdesf2a3)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][4]/CLK (fdesf2a3)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][5]
(recovery check against rising-edge clock SYS_2x_CLK)
Path Group: **async_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.54 2.54
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CLK (fdmf2a3)
0.00 2.54 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/Q (fdmf2a3)
0.63 3.18 r
I_ORCA_TOP/I_RESET_BLOCK/U79/Y (ao1e9) 0.42 3.60 r
I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n (RESET_BLOCK) 0.00 3.60 r
I_ORCA_TOP/I_RST_SOURCE_SYS_2x/Y (clk1a27) 0.30 3.90 r
I_ORCA_TOP/CTS_sys_2x_rst_L1I32198/Y (clk1a27) 0.32 4.22 r
I_ORCA_TOP/CTS_sys_2x_rst_L2I32205/Y (clk1a27) 0.35 4.58 r
I_ORCA_TOP/CTS_sys_2x_rst_L3I32267/Y (clk1a27) 0.30 4.88 r
I_ORCA_TOP/CTS_sys_2x_rst_L4I32348/Y (buf1a6) 0.10 4.98 r
I_ORCA_TOP/I_RISC_CORE/reset_nae (RISC_CORE) 0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/reset_nr (REG_FILE)
0.00 4.98 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U138/Y (inv1a1) 0.07 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U443/Y (inv1a1) 0.28 5.32 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][5]/CLR (fdesf2a3)
0.00 5.32 r
data arrival time 5.32
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.51 7.51
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Reg_Array_reg[1][5]/CLK (fdesf2a3)
7.51 r
library recovery time 0.00 7.51
data required time 7.51
------------------------------------------------------------------------------
data required time 7.51
data arrival time -5.32
------------------------------------------------------------------------------
slack (MET) 2.19
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_0_reg[29]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1178
(falling clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.04 2.04
I_ORCA_TOP/I_SDRAM_IF/DQ_out_0_reg[29]/CLK (fdmf1a3)
0.00 2.04 r
I_ORCA_TOP/I_SDRAM_IF/DQ_out_0_reg[29]/Q (fdmf1a3) 0.74 2.78 f
I_ORCA_TOP/I_SDRAM_IF/U1178/D0 (mx2a15) 0.00 2.78 f
data arrival time 2.78
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.89 5.64
I_ORCA_TOP/I_SDRAM_IF/U1178/S (mx2a15) 5.64 f
clock gating setup time 0.00 5.64
data required time 5.64
------------------------------------------------------------------------------
data required time 5.64
data arrival time -2.78
------------------------------------------------------------------------------
slack (MET) 2.86
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_0_reg[0]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1199
(falling clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.04 2.04
I_ORCA_TOP/I_SDRAM_IF/DQ_out_0_reg[0]/CLK (fdmf1a3) 0.00 2.04 r
I_ORCA_TOP/I_SDRAM_IF/DQ_out_0_reg[0]/Q (fdmf1a3) 0.71 2.76 f
I_ORCA_TOP/I_SDRAM_IF/U1199/D0 (mx2a15) 0.00 2.76 f
data arrival time 2.76
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.89 5.64
I_ORCA_TOP/I_SDRAM_IF/U1199/S (mx2a15) 5.64 f
clock gating setup time 0.00 5.64
data required time 5.64
------------------------------------------------------------------------------
data required time 5.64
data arrival time -2.76
------------------------------------------------------------------------------
slack (MET) 2.88
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[12]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1196
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.51 5.26
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[12]/CLK (fdmf1b6)
0.00 5.26 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[12]/Q (fdmf1b6) 0.57 5.84 r
I_ORCA_TOP/I_SDRAM_IF/U1196/D1 (mx2a15) 0.00 5.84 r
data arrival time 5.84
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.45 8.95
I_ORCA_TOP/I_SDRAM_IF/U1196/S (mx2a15) 8.95 r
clock gating setup time 0.00 8.95
data required time 8.95
------------------------------------------------------------------------------
data required time 8.95
data arrival time -5.84
------------------------------------------------------------------------------
slack (MET) 3.11
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[27]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1180
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.53 5.28
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[27]/CLK (fdmf1b6)
0.00 5.28 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[27]/Q (fdmf1b6) 0.58 5.86 r
I_ORCA_TOP/I_SDRAM_IF/U1180/D1 (mx2a15) 0.00 5.86 r
data arrival time 5.86
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.49 8.99
I_ORCA_TOP/I_SDRAM_IF/U1180/S (mx2a15) 8.99 r
clock gating setup time 0.00 8.99
data required time 8.99
------------------------------------------------------------------------------
data required time 8.99
data arrival time -5.86
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[15]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1193
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.53 5.28
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[15]/CLK (fdmf1b6)
0.00 5.28 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[15]/Q (fdmf1b6) 0.58 5.86 r
I_ORCA_TOP/I_SDRAM_IF/U1193/D1 (mx2a15) 0.00 5.86 r
data arrival time 5.86
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.49 8.99
I_ORCA_TOP/I_SDRAM_IF/U1193/S (mx2a15) 8.99 r
clock gating setup time 0.00 8.99
data required time 8.99
------------------------------------------------------------------------------
data required time 8.99
data arrival time -5.86
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[25]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1182
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.55 5.30
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[25]/CLK (fdmf1b6)
0.00 5.30 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[25]/Q (fdmf1b6) 0.59 5.89 r
I_ORCA_TOP/I_SDRAM_IF/U1182/D1 (mx2a15) 0.00 5.89 r
data arrival time 5.89
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.52 9.02
I_ORCA_TOP/I_SDRAM_IF/U1182/S (mx2a15) 9.02 r
clock gating setup time 0.00 9.02
data required time 9.02
------------------------------------------------------------------------------
data required time 9.02
data arrival time -5.89
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[17]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1191
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.55 5.30
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[17]/CLK (fdmf1b6)
0.00 5.30 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[17]/Q (fdmf1b6) 0.59 5.89 r
I_ORCA_TOP/I_SDRAM_IF/U1191/D1 (mx2a15) 0.00 5.89 r
data arrival time 5.89
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.52 9.02
I_ORCA_TOP/I_SDRAM_IF/U1191/S (mx2a15) 9.02 r
clock gating setup time 0.00 9.02
data required time 9.02
------------------------------------------------------------------------------
data required time 9.02
data arrival time -5.89
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[21]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1186
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.56 5.31
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[21]/CLK (fdmf1b6)
0.00 5.31 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[21]/Q (fdmf1b6) 0.60 5.90 r
I_ORCA_TOP/I_SDRAM_IF/U1186/D1 (mx2a15) 0.00 5.90 r
data arrival time 5.90
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.53 9.03
I_ORCA_TOP/I_SDRAM_IF/U1186/S (mx2a15) 9.03 r
clock gating setup time 0.00 9.03
data required time 9.03
------------------------------------------------------------------------------
data required time 9.03
data arrival time -5.90
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[24]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1183
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.55 5.30
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[24]/CLK (fdmf1b6)
0.00 5.30 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[24]/Q (fdmf1b6) 0.59 5.88 r
I_ORCA_TOP/I_SDRAM_IF/U1183/D1 (mx2a15) 0.00 5.89 r
data arrival time 5.89
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.52 9.02
I_ORCA_TOP/I_SDRAM_IF/U1183/S (mx2a15) 9.02 r
clock gating setup time 0.00 9.02
data required time 9.02
------------------------------------------------------------------------------
data required time 9.02
data arrival time -5.89
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[11]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1197
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.55 5.30
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[11]/CLK (fdmf1b6)
0.00 5.30 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[11]/Q (fdmf1b6) 0.59 5.88 r
I_ORCA_TOP/I_SDRAM_IF/U1197/D1 (mx2a15) 0.00 5.89 r
data arrival time 5.89
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.52 9.02
I_ORCA_TOP/I_SDRAM_IF/U1197/S (mx2a15) 9.02 r
clock gating setup time 0.00 9.02
data required time 9.02
------------------------------------------------------------------------------
data required time 9.02
data arrival time -5.89
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[4]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1173
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.55 5.30
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[4]/CLK (fdmf1b6) 0.00 5.30 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[4]/Q (fdmf1b6) 0.59 5.89 r
I_ORCA_TOP/I_SDRAM_IF/U1173/D1 (mx2a15) 0.00 5.89 r
data arrival time 5.89
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.52 9.02
I_ORCA_TOP/I_SDRAM_IF/U1173/S (mx2a15) 9.02 r
clock gating setup time 0.00 9.02
data required time 9.02
------------------------------------------------------------------------------
data required time 9.02
data arrival time -5.89
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[1]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1188
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.55 5.30
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[1]/CLK (fdmf1b6) 0.00 5.30 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[1]/Q (fdmf1b6) 0.59 5.89 r
I_ORCA_TOP/I_SDRAM_IF/U1188/D1 (mx2a15) 0.00 5.89 r
data arrival time 5.89
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.52 9.02
I_ORCA_TOP/I_SDRAM_IF/U1188/S (mx2a15) 9.02 r
clock gating setup time 0.00 9.02
data required time 9.02
------------------------------------------------------------------------------
data required time 9.02
data arrival time -5.89
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[18]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1190
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.55 5.30
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[18]/CLK (fdmf1b6)
0.00 5.30 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[18]/Q (fdmf1b6) 0.59 5.89 r
I_ORCA_TOP/I_SDRAM_IF/U1190/D1 (mx2a15) 0.00 5.89 r
data arrival time 5.89
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.52 9.02
I_ORCA_TOP/I_SDRAM_IF/U1190/S (mx2a15) 9.02 r
clock gating setup time 0.00 9.02
data required time 9.02
------------------------------------------------------------------------------
data required time 9.02
data arrival time -5.89
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[16]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1192
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.55 5.30
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[16]/CLK (fdmf1b6)
0.00 5.30 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[16]/Q (fdmf1b6) 0.59 5.89 r
I_ORCA_TOP/I_SDRAM_IF/U1192/D1 (mx2a15) 0.00 5.89 r
data arrival time 5.89
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.52 9.02
I_ORCA_TOP/I_SDRAM_IF/U1192/S (mx2a15) 9.02 r
clock gating setup time 0.00 9.02
data required time 9.02
------------------------------------------------------------------------------
data required time 9.02
data arrival time -5.89
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[13]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/U1195
(rising clock gating-check end-point clocked by SDRAM_CLK)
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.56 5.31
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[13]/CLK (fdmf1b6)
0.00 5.31 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[13]/Q (fdmf1b6) 0.59 5.90 r
I_ORCA_TOP/I_SDRAM_IF/U1195/D1 (mx2a15) 0.00 5.90 r
data arrival time 5.90
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.53 9.03
I_ORCA_TOP/I_SDRAM_IF/U1195/S (mx2a15) 9.03 r
clock gating setup time 0.00 9.03
data required time 9.03
------------------------------------------------------------------------------
data required time 9.03
data arrival time -5.90
------------------------------------------------------------------------------
slack (MET) 3.13
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[0]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[0] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.33 1.33
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[0]/CLK (fdmf2a15) 0.00 1.33 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[0]/Q (fdmf2a15) 0.69 2.03 r
I_ORCA_TOP/I_PCI_CORE/pad_en[0] (PCI_CORE) 0.00 2.03 r
I_ORCA_TOP/pad_en[0] (ORCA_TOP) 0.00 2.03 r
scan_in_or_0/Y (or2a6) 0.29 2.31 r
pad_iopad_0/PAD (PCI66DGZ) 3.74 H 6.05 f
pad[0] (inout) 0.00 + 6.05 f
data arrival time 6.05
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -6.05
------------------------------------------------------------------------------
slack (MET) 6.91
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[4]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[4] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.15 1.15
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[4]/CLK (fdmf2a15) 0.00 1.15 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[4]/Q (fdmf2a15) 0.68 1.83 r
I_ORCA_TOP/I_PCI_CORE/pad_en[4] (PCI_CORE) 0.00 1.83 r
I_ORCA_TOP/pad_en[4] (ORCA_TOP) 0.00 1.83 r
scan_in_or_4/Y (or2a6) 0.29 2.11 r
pad_iopad_4/PAD (PCI66DGZ) 3.74 H 5.85 f
pad[4] (inout) 0.00 + 5.85 f
data arrival time 5.85
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.85
------------------------------------------------------------------------------
slack (MET) 7.11
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[5]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[5] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.15 1.15
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[5]/CLK (fdmf2a15) 0.00 1.15 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[5]/Q (fdmf2a15) 0.68 1.83 r
I_ORCA_TOP/I_PCI_CORE/pad_en[5] (PCI_CORE) 0.00 1.83 r
I_ORCA_TOP/pad_en[5] (ORCA_TOP) 0.00 1.83 r
scan_in_or_5/Y (or2a6) 0.29 2.11 r
pad_iopad_5/PAD (PCI66DGZ) 3.74 H 5.85 f
pad[5] (inout) 0.00 + 5.85 f
data arrival time 5.85
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.85
------------------------------------------------------------------------------
slack (MET) 7.11
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[1]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[1] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.13 1.13
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[1]/CLK (fdmf2a15) 0.00 1.13 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[1]/Q (fdmf2a15) 0.67 1.80 r
I_ORCA_TOP/I_PCI_CORE/pad_en[1] (PCI_CORE) 0.00 1.80 r
I_ORCA_TOP/pad_en[1] (ORCA_TOP) 0.00 1.80 r
scan_in_or_1/Y (or2a6) 0.29 2.09 r
pad_iopad_1/PAD (PCI66DGZ) 3.74 H 5.83 f
pad[1] (inout) 0.00 + 5.83 f
data arrival time 5.83
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.83
------------------------------------------------------------------------------
slack (MET) 7.13
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[2]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[2] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.13 1.13
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[2]/CLK (fdmf2a15) 0.00 1.13 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[2]/Q (fdmf2a15) 0.67 1.80 r
I_ORCA_TOP/I_PCI_CORE/pad_en[2] (PCI_CORE) 0.00 1.80 r
I_ORCA_TOP/pad_en[2] (ORCA_TOP) 0.00 1.80 r
scan_in_or_2/Y (or2a6) 0.29 2.09 r
pad_iopad_2/PAD (PCI66DGZ) 3.74 H 5.83 f
pad[2] (inout) 0.00 + 5.83 f
data arrival time 5.83
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.83
------------------------------------------------------------------------------
slack (MET) 7.13
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[3]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[3] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.13 1.13
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[3]/CLK (fdmf2a15) 0.00 1.13 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[3]/Q (fdmf2a15) 0.67 1.80 r
I_ORCA_TOP/I_PCI_CORE/pad_en[3] (PCI_CORE) 0.00 1.80 r
I_ORCA_TOP/pad_en[3] (ORCA_TOP) 0.00 1.80 r
scan_in_or_3/Y (or2a6) 0.29 2.09 r
pad_iopad_3/PAD (PCI66DGZ) 3.74 H 5.83 f
pad[3] (inout) 0.00 + 5.83 f
data arrival time 5.83
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.83
------------------------------------------------------------------------------
slack (MET) 7.13
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[9]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[9] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.33 1.33
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[9]/CLK (fdmf2a15) 0.00 1.33 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[9]/Q (fdmf2a15) 0.75 2.09 r
I_ORCA_TOP/I_PCI_CORE/pad_en[9] (PCI_CORE) 0.00 2.09 r
I_ORCA_TOP/pad_en[9] (ORCA_TOP) 0.00 2.09 r
pad_iopad_9/PAD (PCI66DGZ) 3.71 H 5.80 f
pad[9] (inout) 0.00 + 5.80 f
data arrival time 5.80
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.80
------------------------------------------------------------------------------
slack (MET) 7.16
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[24]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[24] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.33 1.33
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[24]/CLK (fdmf2a15) 0.00 1.33 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[24]/Q (fdmf2a15) 0.75 2.09 r
I_ORCA_TOP/I_PCI_CORE/pad_en[24] (PCI_CORE) 0.00 2.09 r
I_ORCA_TOP/pad_en[24] (ORCA_TOP) 0.00 2.09 r
pad_iopad_24/PAD (PCI66DGZ) 3.71 H 5.80 f
pad[24] (inout) 0.00 + 5.80 f
data arrival time 5.80
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.80
------------------------------------------------------------------------------
slack (MET) 7.16
Startpoint: I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg[17]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pserr_n (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.33 1.33
I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg[17]/CLK (fdmf2a15)
0.00 1.33 r
I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg[17]/Q (fdmf2a15)
0.75 2.09 r
I_ORCA_TOP/I_PCI_CORE/pserr_n_en (PCI_CORE) 0.00 2.09 r
I_ORCA_TOP/pserr_n_en (ORCA_TOP) 0.00 2.09 r
pserr_n_iopad/PAD (PCI66DGZ) 3.71 H 5.80 f
pserr_n (inout) 0.00 + 5.80 f
data arrival time 5.80
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.80
------------------------------------------------------------------------------
slack (MET) 7.16
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[16]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[16] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.33 1.33
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[16]/CLK (fdmf2a15) 0.00 1.33 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[16]/Q (fdmf2a15) 0.74 2.08 r
I_ORCA_TOP/I_PCI_CORE/pad_en[16] (PCI_CORE) 0.00 2.08 r
I_ORCA_TOP/pad_en[16] (ORCA_TOP) 0.00 2.08 r
pad_iopad_16/PAD (PCI66DGZ) 3.71 H 5.79 f
pad[16] (inout) 0.00 + 5.79 f
data arrival time 5.79
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.79
------------------------------------------------------------------------------
slack (MET) 7.18
Startpoint: I_ORCA_TOP/I_PCI_CORE/pc_be_en_reg[0]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pc_be[0] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.29 1.29
I_ORCA_TOP/I_PCI_CORE/pc_be_en_reg[0]/CLK (fdmf2a15)
0.00 1.29 r
I_ORCA_TOP/I_PCI_CORE/pc_be_en_reg[0]/Q (fdmf2a15) 0.74 2.03 r
I_ORCA_TOP/I_PCI_CORE/pc_be_en[0] (PCI_CORE) 0.00 2.03 r
I_ORCA_TOP/pc_be_en[0] (ORCA_TOP) 0.00 2.03 r
pc_be_iopad_0/PAD (PCI66DGZ) 3.71 H 5.74 f
pc_be[0] (inout) 0.00 + 5.74 f
data arrival time 5.74
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.74
------------------------------------------------------------------------------
slack (MET) 7.22
Startpoint: I_ORCA_TOP/I_PCI_CORE/pc_be_en_reg[1]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pc_be[1] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.29 1.29
I_ORCA_TOP/I_PCI_CORE/pc_be_en_reg[1]/CLK (fdmf2a15)
0.00 1.29 r
I_ORCA_TOP/I_PCI_CORE/pc_be_en_reg[1]/Q (fdmf2a15) 0.74 2.03 r
I_ORCA_TOP/I_PCI_CORE/pc_be_en[1] (PCI_CORE) 0.00 2.03 r
I_ORCA_TOP/pc_be_en[1] (ORCA_TOP) 0.00 2.03 r
pc_be_iopad_1/PAD (PCI66DGZ) 3.71 H 5.74 f
pc_be[1] (inout) 0.00 + 5.74 f
data arrival time 5.74
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.74
------------------------------------------------------------------------------
slack (MET) 7.22
Startpoint: I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg[7]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: ptrdy_n (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.27 1.27
I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg[7]/CLK (fdmf2a15)
0.00 1.27 r
I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg[7]/Q (fdmf2a15)
0.74 2.01 r
I_ORCA_TOP/I_PCI_CORE/ptrdy_n_en (PCI_CORE) 0.00 2.01 r
I_ORCA_TOP/ptrdy_n_en (ORCA_TOP) 0.00 2.01 r
ptrdy_n_iopad/PAD (PCI66DGZ) 3.71 H 5.72 f
ptrdy_n (inout) 0.00 + 5.72 f
data arrival time 5.72
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.72
------------------------------------------------------------------------------
slack (MET) 7.24
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[25]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[25] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.27 1.27
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[25]/CLK (fdmf2a15) 0.00 1.27 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[25]/Q (fdmf2a15) 0.73 2.00 r
I_ORCA_TOP/I_PCI_CORE/pad_en[25] (PCI_CORE) 0.00 2.00 r
I_ORCA_TOP/pad_en[25] (ORCA_TOP) 0.00 2.00 r
pad_iopad_25/PAD (PCI66DGZ) 3.71 H 5.70 f
pad[25] (inout) 0.00 + 5.70 f
data arrival time 5.70
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.70
------------------------------------------------------------------------------
slack (MET) 7.26
Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg[21]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Endpoint: pad[21] (output port clocked by IO_PCI_CLK)
Path Group: IO_PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.15 1.15
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[21]/CLK (fdmf2a15) 0.00 1.15 r
I_ORCA_TOP/I_PCI_CORE/pad_en_reg[21]/Q (fdmf2a15) 0.67 1.82 r
I_ORCA_TOP/I_PCI_CORE/U563/Y (clk1a15) 0.18 2.00 r
I_ORCA_TOP/I_PCI_CORE/pad_en[21] (PCI_CORE) 0.00 2.00 r
I_ORCA_TOP/pad_en[21] (ORCA_TOP) 0.00 2.00 r
pad_iopad_21/PAD (PCI66DGZ) 3.70 H 5.70 f
pad[21] (inout) 0.00 + 5.70 f
data arrival time 5.70
clock IO_PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.96 16.96
output external delay -4.00 12.96
data required time 12.96
------------------------------------------------------------------------------
data required time 12.96
data arrival time -5.70
------------------------------------------------------------------------------
slack (MET) 7.26
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U1261
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U440/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[7] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[7] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U207/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1058/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U1029/Y (mx2d15) 0.26 13.13 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1261/D0 (fdmf1a6) 0.00 13.13 r
data arrival time 13.13
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.26 16.26
I_ORCA_TOP/I_PCI_READ_FIFO/U1261/CLK (fdmf1a6) 16.26 r
library setup time -0.18 16.08
data required time 16.08
------------------------------------------------------------------------------
data required time 16.08
data arrival time -13.13
------------------------------------------------------------------------------
slack (MET) 2.94
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U1021
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U440/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[7] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[7] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U207/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1058/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U1008/Y (mx2d15) 0.26 13.13 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1021/D0 (fdmf1a6) 0.00 13.13 r
data arrival time 13.13
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.26 16.26
I_ORCA_TOP/I_PCI_READ_FIFO/U1021/CLK (fdmf1a6) 16.26 r
library setup time -0.18 16.08
data required time 16.08
------------------------------------------------------------------------------
data required time 16.08
data arrival time -13.13
------------------------------------------------------------------------------
slack (MET) 2.94
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U439
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U438/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[5] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[5] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U205/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1074/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U554/Y (mx2d1) 0.21 13.08 r
I_ORCA_TOP/I_PCI_READ_FIFO/U439/D0 (fdmf1a6) 0.00 13.08 r
data arrival time 13.08
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.24 16.24
I_ORCA_TOP/I_PCI_READ_FIFO/U439/CLK (fdmf1a6) 16.24 r
library setup time -0.21 16.03
data required time 16.03
------------------------------------------------------------------------------
data required time 16.03
data arrival time -13.08
------------------------------------------------------------------------------
slack (MET) 2.95
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U681
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U437/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[4] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[4] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U204/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1059/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U432/Y (mx2d1) 0.21 13.08 r
I_ORCA_TOP/I_PCI_READ_FIFO/U681/D0 (fdmf1a6) 0.00 13.08 r
data arrival time 13.08
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.26 16.26
I_ORCA_TOP/I_PCI_READ_FIFO/U681/CLK (fdmf1a6) 16.26 r
library setup time -0.21 16.05
data required time 16.05
------------------------------------------------------------------------------
data required time 16.05
data arrival time -13.08
------------------------------------------------------------------------------
slack (MET) 2.97
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U445
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U440/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[7] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[7] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U207/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1058/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U552/Y (mx2d1) 0.21 13.08 r
I_ORCA_TOP/I_PCI_READ_FIFO/U445/D0 (fdmf1a3) 0.00 13.08 r
data arrival time 13.08
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.26 16.26
I_ORCA_TOP/I_PCI_READ_FIFO/U445/CLK (fdmf1a3) 16.26 r
library setup time -0.21 16.05
data required time 16.05
------------------------------------------------------------------------------
data required time 16.05
data arrival time -13.08
------------------------------------------------------------------------------
slack (MET) 2.97
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U344
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U438/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[5] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[5] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U205/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1074/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U675/Y (mx2d2) 0.15 13.03 r
I_ORCA_TOP/I_PCI_READ_FIFO/U344/D0 (fdmf1a6) 0.00 13.03 r
data arrival time 13.03
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.24 16.24
I_ORCA_TOP/I_PCI_READ_FIFO/U344/CLK (fdmf1a6) 16.24 r
library setup time -0.20 16.04
data required time 16.04
------------------------------------------------------------------------------
data required time 16.04
data arrival time -13.03
------------------------------------------------------------------------------
slack (MET) 3.02
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U384
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U438/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[5] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[5] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U205/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1074/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U700/Y (mx2d2) 0.15 13.03 r
I_ORCA_TOP/I_PCI_READ_FIFO/U384/D0 (fdmf1a6) 0.00 13.03 r
data arrival time 13.03
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.24 16.24
I_ORCA_TOP/I_PCI_READ_FIFO/U384/CLK (fdmf1a6) 16.24 r
library setup time -0.20 16.04
data required time 16.04
------------------------------------------------------------------------------
data required time 16.04
data arrival time -13.03
------------------------------------------------------------------------------
slack (MET) 3.02
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U447
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U438/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[5] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[5] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U205/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1074/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U725/Y (mx2d2) 0.15 13.03 r
I_ORCA_TOP/I_PCI_READ_FIFO/U447/D0 (fdmf1a6) 0.00 13.03 r
data arrival time 13.03
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.24 16.24
I_ORCA_TOP/I_PCI_READ_FIFO/U447/CLK (fdmf1a6) 16.24 r
library setup time -0.20 16.04
data required time 16.04
------------------------------------------------------------------------------
data required time 16.04
data arrival time -13.03
------------------------------------------------------------------------------
slack (MET) 3.02
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U1310
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U440/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[7] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[7] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U207/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1058/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U730/Y (mx2d2) 0.15 13.03 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1310/D0 (fdmf1a6) 0.00 13.03 r
data arrival time 13.03
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.24 16.24
I_ORCA_TOP/I_PCI_READ_FIFO/U1310/CLK (fdmf1a6) 16.24 r
library setup time -0.20 16.04
data required time 16.04
------------------------------------------------------------------------------
data required time 16.04
data arrival time -13.03
------------------------------------------------------------------------------
slack (MET) 3.02
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U2331
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U437/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[4] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[4] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U204/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1059/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U615/Y (mx2d2) 0.15 13.03 r
I_ORCA_TOP/I_PCI_READ_FIFO/U2331/D0 (fdmf1a6) 0.00 13.03 r
data arrival time 13.03
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.24 16.24
I_ORCA_TOP/I_PCI_READ_FIFO/U2331/CLK (fdmf1a6) 16.24 r
library setup time -0.20 16.04
data required time 16.04
------------------------------------------------------------------------------
data required time 16.04
data arrival time -13.03
------------------------------------------------------------------------------
slack (MET) 3.02
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U4311
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U434/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[1] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[1] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U201/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1077/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U719/Y (mx2d2) 0.15 13.03 r
I_ORCA_TOP/I_PCI_READ_FIFO/U4311/D0 (fdmf1a6) 0.00 13.03 r
data arrival time 13.03
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.24 16.24
I_ORCA_TOP/I_PCI_READ_FIFO/U4311/CLK (fdmf1a6) 16.24 r
library setup time -0.20 16.04
data required time 16.04
------------------------------------------------------------------------------
data required time 16.04
data arrival time -13.03
------------------------------------------------------------------------------
slack (MET) 3.02
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U1101
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U438/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[5] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[5] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U205/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1074/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U10311/Y (mx2d15) 0.26 13.13 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1101/D0 (fdmf1a6) 0.00 13.13 r
data arrival time 13.13
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.33 16.33
I_ORCA_TOP/I_PCI_READ_FIFO/U1101/CLK (fdmf1a6) 16.33 r
library setup time -0.18 16.15
data required time 16.15
------------------------------------------------------------------------------
data required time 16.15
data arrival time -13.13
------------------------------------------------------------------------------
slack (MET) 3.02
Startpoint: pc_be[0] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U1171
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[0] (inout) 0.00 + 9.96 r
pc_be_iopad_0/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_0/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[0] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[0] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U492/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U498/Y (or3a15) 0.34 11.29 f
I_ORCA_TOP/I_PCI_CORE/U499/Y (ao1f15) 0.44 11.73 r
I_ORCA_TOP/I_PCI_CORE/U537/Y (inv1a1) 0.12 11.85 f
I_ORCA_TOP/I_PCI_CORE/U538/Y (ao2i15) 0.36 12.21 r
I_ORCA_TOP/I_PCI_CORE/U434/Y (and2a15) 0.17 12.39 r
I_ORCA_TOP/I_PCI_CORE/read_data[1] (PCI_CORE) 0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[1] (PCI_RFIFO)
0.00 12.39 r
I_ORCA_TOP/I_PCI_READ_FIFO/U201/Y (clk1a3) 0.38 12.76 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1077/Y (inv1a27) 0.11 12.87 f
I_ORCA_TOP/I_PCI_READ_FIFO/U1040/Y (mx2d15) 0.26 13.13 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1171/D0 (fdmf1a6) 0.00 13.13 r
data arrival time 13.13
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.33 16.33
I_ORCA_TOP/I_PCI_READ_FIFO/U1171/CLK (fdmf1a6) 16.33 r
library setup time -0.18 16.15
data required time 16.15
------------------------------------------------------------------------------
data required time 16.15
data arrival time -13.13
------------------------------------------------------------------------------
slack (MET) 3.02
Startpoint: pc_be[2] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U971
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[2] (inout) 0.00 + 9.96 r
pc_be_iopad_2/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_2/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[2] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[2] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U493/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U495/Y (or3a15) 0.37 11.32 f
I_ORCA_TOP/I_PCI_CORE/U257/Y (oa1a3) 0.33 11.65 f
I_ORCA_TOP/I_PCI_CORE/U536/Y (ao1f15) 0.45 12.10 r
I_ORCA_TOP/I_PCI_CORE/U443/Y (and2a15) 0.19 12.28 r
I_ORCA_TOP/I_PCI_CORE/read_data[10] (PCI_CORE) 0.00 12.28 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[10] (PCI_RFIFO)
0.00 12.28 r
I_ORCA_TOP/I_PCI_READ_FIFO/U210/Y (clk1a3) 0.38 12.66 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1073/Y (inv1a27) 0.11 12.77 f
I_ORCA_TOP/I_PCI_READ_FIFO/U1045/Y (mx2d15) 0.26 13.03 r
I_ORCA_TOP/I_PCI_READ_FIFO/U971/D0 (fdmf1a6) 0.00 13.03 r
data arrival time 13.03
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.24 16.24
I_ORCA_TOP/I_PCI_READ_FIFO/U971/CLK (fdmf1a6) 16.24 r
library setup time -0.18 16.06
data required time 16.06
------------------------------------------------------------------------------
data required time 16.06
data arrival time -13.03
------------------------------------------------------------------------------
slack (MET) 3.02
Startpoint: pc_be[2] (input port clocked by IO_PCI_CLK)
Endpoint: I_ORCA_TOP/I_PCI_READ_FIFO/U1212
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock IO_PCI_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.96 1.96
input external delay 8.00 9.96 r
pc_be[2] (inout) 0.00 + 9.96 r
pc_be_iopad_2/PAD (PCI66DGZ) 0.00 + 9.96 r
pc_be_iopad_2/C (PCI66DGZ) 0.94 10.90 r
I_ORCA_TOP/pc_be_in[2] (ORCA_TOP) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/pc_be_in[2] (PCI_CORE) 0.00 10.90 r
I_ORCA_TOP/I_PCI_CORE/U493/Y (inv1a27) 0.05 10.95 f
I_ORCA_TOP/I_PCI_CORE/U495/Y (or3a15) 0.37 11.32 f
I_ORCA_TOP/I_PCI_CORE/U257/Y (oa1a3) 0.33 11.65 f
I_ORCA_TOP/I_PCI_CORE/U536/Y (ao1f15) 0.45 12.10 r
I_ORCA_TOP/I_PCI_CORE/U443/Y (and2a15) 0.19 12.28 r
I_ORCA_TOP/I_PCI_CORE/read_data[10] (PCI_CORE) 0.00 12.28 r
I_ORCA_TOP/I_PCI_READ_FIFO/fifo_data_in[10] (PCI_RFIFO)
0.00 12.28 r
I_ORCA_TOP/I_PCI_READ_FIFO/U210/Y (clk1a3) 0.38 12.66 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1073/Y (inv1a27) 0.11 12.77 f
I_ORCA_TOP/I_PCI_READ_FIFO/U1027/Y (mx2d15) 0.26 13.03 r
I_ORCA_TOP/I_PCI_READ_FIFO/U1212/D0 (fdmf1a6) 0.00 13.03 r
data arrival time 13.03
clock PCI_CLK (rise edge) 15.00 15.00
clock network delay (propagated) 1.24 16.24
I_ORCA_TOP/I_PCI_READ_FIFO/U1212/CLK (fdmf1a6) 16.24 r
library setup time -0.18 16.06
data required time 16.06
------------------------------------------------------------------------------
data required time 16.06
data arrival time -13.03
------------------------------------------------------------------------------
slack (MET) 3.02
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U201
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[27]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U201/CLK (fdmf2a15) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U201/Q (fdmf2a15) 0.75 2.22 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1282/Y (inv1a9) 0.26 2.48 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1272/Y (or2c2) 0.29 2.77 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1602/Y (buf1a9) 0.37 3.14 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6710/Y (and2c1) 0.13 3.27 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6610/Y (and2c1) 0.54 3.81 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1642/Y (or3d2) 0.25 4.06 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[27] (SDRAM_WFIFO)
0.00 4.06 f
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[27] (SDRAM_IF) 0.00 4.06 f
I_ORCA_TOP/I_SDRAM_IF/U1314/Y (clk1b2) 0.20 4.26 r
I_ORCA_TOP/I_SDRAM_IF/U1315/Y (inv1a6) 0.07 4.32 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[27]/D0 (fdmf1b6) 0.00 4.32 f
data arrival time 4.32
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.53 5.28
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[27]/CLK (fdmf1b6) 5.28 f
library setup time -0.24 5.03
data required time 5.03
------------------------------------------------------------------------------
data required time 5.03
data arrival time -4.32
------------------------------------------------------------------------------
slack (MET) 0.71
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[15]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/CLK (fdmf2a6) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/Q (fdmf2a6) 0.65 2.12 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3891/Y (clk1b3) 0.15 2.27 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3921/Y (and2a6) 0.27 2.54 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U846/Y (and2a9) 0.26 2.81 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U271/Y (clk1a27) 0.37 3.17 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2312/Y (or2c3) 0.20 3.37 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6461/Y (or2c15) 0.13 3.50 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6471/Y (and3d15) 0.05 3.56 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2082/Y (or3d1) 0.22 3.77 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U146/Y (inv1a1) 0.11 3.88 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U145/Y (inv1a1) 0.41 4.30 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[15] (SDRAM_WFIFO)
0.00 4.30 r
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[15] (SDRAM_IF) 0.00 4.30 r
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[15]/D0 (fdmf1b6) 0.00 4.30 r
data arrival time 4.30
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.53 5.28
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[15]/CLK (fdmf1b6) 5.28 f
library setup time -0.23 5.05
data required time 5.05
------------------------------------------------------------------------------
data required time 5.05
data arrival time -4.30
------------------------------------------------------------------------------
slack (MET) 0.75
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[13]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/CLK (fdmf2a6) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/Q (fdmf2a6) 0.65 2.12 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3891/Y (clk1b3) 0.14 2.26 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U269/Y (and2a9) 0.24 2.49 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U268/Y (and2a6) 0.23 2.72 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6841/Y (buf1a27) 0.20 2.92 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U85/Y (or2c2) 0.28 3.20 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6541/Y (or2c15) 0.11 3.31 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6551/Y (and3d15) 0.13 3.43 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2062/Y (or3d1) 0.23 3.66 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U142/Y (inv1a1) 0.28 3.94 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1411/Y (inv1a3) 0.14 4.08 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[13] (SDRAM_WFIFO)
0.00 4.08 f
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[13] (SDRAM_IF) 0.00 4.08 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[13]/D0 (fdmf1b6) 0.00 4.08 f
data arrival time 4.08
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.56 5.31
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[13]/CLK (fdmf1b6) 5.31 f
library setup time -0.25 5.06
data required time 5.06
------------------------------------------------------------------------------
data required time 5.06
data arrival time -4.08
------------------------------------------------------------------------------
slack (MET) 0.98
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[26]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/CLK (fdmf2a6) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/Q (fdmf2a6) 0.65 2.12 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3891/Y (clk1b3) 0.14 2.26 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U269/Y (and2a9) 0.24 2.49 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U268/Y (and2a6) 0.23 2.72 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6841/Y (buf1a27) 0.20 2.92 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U5610/Y (or2c1) 0.19 3.11 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U5410/Y (or2c1) 0.30 3.41 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1532/Y (and3d6) 0.27 3.68 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U4381/Y (or3d6) 0.15 3.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[26] (SDRAM_WFIFO)
0.00 3.83 f
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[26] (SDRAM_IF) 0.00 3.83 f
I_ORCA_TOP/I_SDRAM_IF/U1300/Y (buf1a27) 0.18 4.00 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[26]/D0 (fdmf1b6) 0.00 4.00 f
data arrival time 4.00
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.50 5.25
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[26]/CLK (fdmf1b6) 5.25 f
library setup time -0.25 5.00
data required time 5.00
------------------------------------------------------------------------------
data required time 5.00
data arrival time -4.00
------------------------------------------------------------------------------
slack (MET) 1.00
Startpoint: I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/out_control_reg[27]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.61 1.61
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/CLK (fdmf1a3)
0.00 1.61 r
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/Q (fdmf1a3)
0.65 2.26 r
I_ORCA_TOP/I_SDRAM_IF/U707/Y (clk1b3) 0.22 2.48 f
I_ORCA_TOP/I_SDRAM_IF/U1133/Y (or3a15) 0.40 2.88 f
I_ORCA_TOP/I_SDRAM_IF/U1216/Y (inv1a27) 0.06 2.94 r
I_ORCA_TOP/I_SDRAM_IF/U1134/Y (or3c15) 0.28 3.22 f
I_ORCA_TOP/I_SDRAM_IF/U691/Y (clk1b3) 0.13 3.35 r
I_ORCA_TOP/I_SDRAM_IF/U664/Y (or3c3) 0.59 3.94 f
I_ORCA_TOP/I_SDRAM_IF/U1217/Y (inv1a27) 0.11 4.05 r
I_ORCA_TOP/I_SDRAM_IF/U684/Y (or2c9) 0.23 4.28 f
I_ORCA_TOP/I_SDRAM_IF/U1122/Y (or2c15) 0.15 4.42 r
I_ORCA_TOP/I_SDRAM_IF/U670/Y (or2a6) 0.32 4.74 r
I_ORCA_TOP/I_SDRAM_IF/U1114/Y (or2a15) 0.24 4.98 r
I_ORCA_TOP/I_SDRAM_IF/U1226/Y (or2a15) 0.20 5.18 r
I_ORCA_TOP/I_SDRAM_IF/U1111/Y (and2a1) 0.37 5.55 r
I_ORCA_TOP/I_SDRAM_IF/IU504/Y (or2c2) 0.27 5.82 f
I_ORCA_TOP/I_SDRAM_IF/IU546/Y (ao1f2) 0.36 6.18 r
I_ORCA_TOP/I_SDRAM_IF/IU548/Y (oa1f6) 0.11 6.29 f
I_ORCA_TOP/I_SDRAM_IF/U45/Y (and2c2) 0.29 6.58 r
I_ORCA_TOP/I_SDRAM_IF/U30/Y (oa1f6) 0.18 6.76 f
I_ORCA_TOP/I_SDRAM_IF/U1232/Y (clk1b6) 0.12 6.88 r
I_ORCA_TOP/I_SDRAM_IF/U1233/Y (or2c2) 0.19 7.07 f
I_ORCA_TOP/I_SDRAM_IF/U1229/Y (ao1f3) 0.27 7.34 r
I_ORCA_TOP/I_SDRAM_IF/IU858/Y (xor2b2) 0.23 7.57 r
I_ORCA_TOP/I_SDRAM_IF/U748/Y (ao4e9) 0.39 7.95 r
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[27]/D0 (fdmf2a6)
0.00 7.95 r
data arrival time 7.95
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.63 9.13
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[27]/CLK (fdmf2a6) 9.13 r
library setup time -0.14 8.99
data required time 8.99
------------------------------------------------------------------------------
data required time 8.99
data arrival time -7.95
------------------------------------------------------------------------------
slack (MET) 1.03
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[1]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/CLK (fdmf2a6) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/Q (fdmf2a6) 0.65 2.12 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3891/Y (clk1b3) 0.14 2.26 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U269/Y (and2a9) 0.24 2.49 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U268/Y (and2a6) 0.23 2.72 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6851/Y (buf1a27) 0.20 2.93 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U257/Y (or2c2) 0.28 3.20 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6291/Y (or2c15) 0.07 3.28 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2313/Y (and3d2) 0.28 3.56 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2282/Y (or3d3) 0.23 3.79 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[1] (SDRAM_WFIFO)
0.00 3.79 f
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[1] (SDRAM_IF) 0.00 3.79 f
I_ORCA_TOP/I_SDRAM_IF/U1354/Y (buf1a27) 0.21 4.00 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[1]/D0 (fdmf1b6) 0.00 4.00 f
data arrival time 4.00
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.55 5.30
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[1]/CLK (fdmf1b6) 5.30 f
library setup time -0.23 5.07
data required time 5.07
------------------------------------------------------------------------------
data required time 5.07
data arrival time -4.00
------------------------------------------------------------------------------
slack (MET) 1.07
Startpoint: I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/out_control_reg[25]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.61 1.61
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/CLK (fdmf1a3)
0.00 1.61 r
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/Q (fdmf1a3)
0.65 2.26 r
I_ORCA_TOP/I_SDRAM_IF/U707/Y (clk1b3) 0.22 2.48 f
I_ORCA_TOP/I_SDRAM_IF/U1133/Y (or3a15) 0.40 2.88 f
I_ORCA_TOP/I_SDRAM_IF/U1216/Y (inv1a27) 0.06 2.94 r
I_ORCA_TOP/I_SDRAM_IF/U1134/Y (or3c15) 0.28 3.22 f
I_ORCA_TOP/I_SDRAM_IF/U691/Y (clk1b3) 0.13 3.35 r
I_ORCA_TOP/I_SDRAM_IF/U664/Y (or3c3) 0.59 3.94 f
I_ORCA_TOP/I_SDRAM_IF/U1217/Y (inv1a27) 0.11 4.05 r
I_ORCA_TOP/I_SDRAM_IF/U684/Y (or2c9) 0.23 4.28 f
I_ORCA_TOP/I_SDRAM_IF/U1122/Y (or2c15) 0.15 4.42 r
I_ORCA_TOP/I_SDRAM_IF/U670/Y (or2a6) 0.32 4.74 r
I_ORCA_TOP/I_SDRAM_IF/U1114/Y (or2a15) 0.24 4.98 r
I_ORCA_TOP/I_SDRAM_IF/U1226/Y (or2a15) 0.20 5.18 r
I_ORCA_TOP/I_SDRAM_IF/U1111/Y (and2a1) 0.37 5.55 r
I_ORCA_TOP/I_SDRAM_IF/IU504/Y (or2c2) 0.27 5.82 f
I_ORCA_TOP/I_SDRAM_IF/IU546/Y (ao1f2) 0.36 6.18 r
I_ORCA_TOP/I_SDRAM_IF/IU548/Y (oa1f6) 0.11 6.29 f
I_ORCA_TOP/I_SDRAM_IF/U45/Y (and2c2) 0.29 6.58 r
I_ORCA_TOP/I_SDRAM_IF/U30/Y (oa1f6) 0.18 6.76 f
I_ORCA_TOP/I_SDRAM_IF/U1232/Y (clk1b6) 0.12 6.88 r
I_ORCA_TOP/I_SDRAM_IF/U1231/Y (or2c3) 0.14 7.02 f
I_ORCA_TOP/I_SDRAM_IF/U1230/Y (ao1f3) 0.26 7.28 r
I_ORCA_TOP/I_SDRAM_IF/IU799/Y (xor2b2) 0.23 7.51 r
I_ORCA_TOP/I_SDRAM_IF/U745/Y (ao4e9) 0.39 7.90 r
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[25]/D0 (fdmf2a6)
0.00 7.90 r
data arrival time 7.90
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.62 9.12
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[25]/CLK (fdmf2a6) 9.12 r
library setup time -0.14 8.97
data required time 8.97
------------------------------------------------------------------------------
data required time 8.97
data arrival time -7.90
------------------------------------------------------------------------------
slack (MET) 1.08
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[12]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/CLK (fdmf2a6) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/Q (fdmf2a6) 0.65 2.12 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3891/Y (clk1b3) 0.14 2.26 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3921/Y (and2a6) 0.23 2.49 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U846/Y (and2a9) 0.23 2.72 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U271/Y (clk1a27) 0.36 3.08 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U208/Y (or2c2) 0.28 3.35 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6581/Y (or2c15) 0.12 3.48 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6591/Y (and3d15) 0.15 3.63 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2052/Y (or3d6) 0.14 3.77 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[12] (SDRAM_WFIFO)
0.00 3.77 f
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[12] (SDRAM_IF) 0.00 3.77 f
I_ORCA_TOP/I_SDRAM_IF/U1320/Y (buf1a27) 0.17 3.94 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[12]/D0 (fdmf1b6) 0.00 3.94 f
data arrival time 3.94
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.51 5.26
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[12]/CLK (fdmf1b6) 5.26 f
library setup time -0.24 5.02
data required time 5.02
------------------------------------------------------------------------------
data required time 5.02
data arrival time -3.94
------------------------------------------------------------------------------
slack (MET) 1.08
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[6]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/CLK (fdmf2a6) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/Q (fdmf2a6) 0.65 2.12 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3891/Y (clk1b3) 0.14 2.26 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3921/Y (and2a6) 0.23 2.49 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U846/Y (and2a9) 0.23 2.72 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U271/Y (clk1a27) 0.36 3.08 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U244/Y (or2c3) 0.20 3.28 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U5871/Y (or2c15) 0.07 3.35 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2122/Y (and3d2) 0.28 3.63 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2092/Y (or3d3) 0.23 3.86 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[6] (SDRAM_WFIFO)
0.00 3.86 f
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[6] (SDRAM_IF) 0.00 3.86 f
I_ORCA_TOP/I_SDRAM_IF/U1362/Y (buf1a27) 0.21 4.07 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[6]/D0 (fdmf1b6) 0.00 4.07 f
data arrival time 4.07
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.63 5.38
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[6]/CLK (fdmf1b6) 5.38 f
library setup time -0.23 5.15
data required time 5.15
------------------------------------------------------------------------------
data required time 5.15
data arrival time -4.07
------------------------------------------------------------------------------
slack (MET) 1.08
Startpoint: I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/out_control_reg[30]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.61 1.61
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/CLK (fdmf1a3)
0.00 1.61 r
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/Q (fdmf1a3)
0.65 2.26 r
I_ORCA_TOP/I_SDRAM_IF/U707/Y (clk1b3) 0.22 2.48 f
I_ORCA_TOP/I_SDRAM_IF/U1133/Y (or3a15) 0.40 2.88 f
I_ORCA_TOP/I_SDRAM_IF/U1216/Y (inv1a27) 0.06 2.94 r
I_ORCA_TOP/I_SDRAM_IF/U1134/Y (or3c15) 0.28 3.22 f
I_ORCA_TOP/I_SDRAM_IF/U691/Y (clk1b3) 0.13 3.35 r
I_ORCA_TOP/I_SDRAM_IF/U664/Y (or3c3) 0.59 3.94 f
I_ORCA_TOP/I_SDRAM_IF/U1217/Y (inv1a27) 0.11 4.05 r
I_ORCA_TOP/I_SDRAM_IF/U684/Y (or2c9) 0.23 4.28 f
I_ORCA_TOP/I_SDRAM_IF/U1122/Y (or2c15) 0.15 4.42 r
I_ORCA_TOP/I_SDRAM_IF/U670/Y (or2a6) 0.32 4.74 r
I_ORCA_TOP/I_SDRAM_IF/U1114/Y (or2a15) 0.24 4.98 r
I_ORCA_TOP/I_SDRAM_IF/U1226/Y (or2a15) 0.20 5.18 r
I_ORCA_TOP/I_SDRAM_IF/U1111/Y (and2a1) 0.37 5.55 r
I_ORCA_TOP/I_SDRAM_IF/IU504/Y (or2c2) 0.27 5.82 f
I_ORCA_TOP/I_SDRAM_IF/IU546/Y (ao1f2) 0.36 6.18 r
I_ORCA_TOP/I_SDRAM_IF/IU548/Y (oa1f6) 0.11 6.29 f
I_ORCA_TOP/I_SDRAM_IF/U45/Y (and2c2) 0.29 6.58 r
I_ORCA_TOP/I_SDRAM_IF/U30/Y (oa1f6) 0.18 6.76 f
I_ORCA_TOP/I_SDRAM_IF/IU880/Y (ao1f6) 0.23 6.99 r
I_ORCA_TOP/I_SDRAM_IF/U52/Y (and2a1) 0.26 7.25 r
I_ORCA_TOP/I_SDRAM_IF/U51/Y (xor2a1) 0.22 7.47 r
I_ORCA_TOP/I_SDRAM_IF/U1126/Y (ao4e15) 0.41 7.88 r
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[30]/D0 (fdmf2a6)
0.00 7.88 r
data arrival time 7.88
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.61 9.11
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[30]/CLK (fdmf2a6) 9.11 r
library setup time -0.14 8.97
data required time 8.97
------------------------------------------------------------------------------
data required time 8.97
data arrival time -7.88
------------------------------------------------------------------------------
slack (MET) 1.09
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U201
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[28]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U201/CLK (fdmf2a15) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U201/Q (fdmf2a15) 0.69 2.16 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1282/Y (inv1a9) 0.35 2.52 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U4012/Y (or2c6) 0.23 2.75 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U4212/Y (buf1a27) 0.23 2.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U8010/Y (and2c1) 0.55 3.53 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U7710/Y (and2c3) 0.14 3.68 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1652/Y (or3d2) 0.23 3.91 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[28] (SDRAM_WFIFO)
0.00 3.91 r
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[28] (SDRAM_IF) 0.00 3.91 r
I_ORCA_TOP/I_SDRAM_IF/U1329/Y (buf1a27) 0.16 4.06 r
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[28]/D0 (fdmf1b6) 0.00 4.06 r
data arrival time 4.06
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.56 5.31
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[28]/CLK (fdmf1b6) 5.31 f
library setup time -0.13 5.18
data required time 5.18
------------------------------------------------------------------------------
data required time 5.18
data arrival time -4.06
------------------------------------------------------------------------------
slack (MET) 1.12
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U201
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[11]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U201/CLK (fdmf2a15) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U201/Q (fdmf2a15) 0.75 2.22 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1282/Y (inv1a9) 0.26 2.48 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1272/Y (or2c2) 0.29 2.77 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1602/Y (buf1a9) 0.37 3.14 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2013/Y (and2c3) 0.09 3.24 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1942/Y (and2c3) 0.37 3.60 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U4371/Y (or3d15) 0.12 3.73 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U139/Y (clk1a3) 0.20 3.93 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[11] (SDRAM_WFIFO)
0.00 3.93 f
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[11] (SDRAM_IF) 0.00 3.93 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[11]/D0 (fdmf1b6) 0.00 3.93 f
data arrival time 3.93
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.55 5.30
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[11]/CLK (fdmf1b6) 5.30 f
library setup time -0.24 5.05
data required time 5.05
------------------------------------------------------------------------------
data required time 5.05
data arrival time -3.93
------------------------------------------------------------------------------
slack (MET) 1.13
Startpoint: I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/out_control_reg[23]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.61 1.61
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/CLK (fdmf1a3)
0.00 1.61 r
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/Q (fdmf1a3)
0.65 2.26 r
I_ORCA_TOP/I_SDRAM_IF/U707/Y (clk1b3) 0.22 2.48 f
I_ORCA_TOP/I_SDRAM_IF/U1133/Y (or3a15) 0.40 2.88 f
I_ORCA_TOP/I_SDRAM_IF/U1216/Y (inv1a27) 0.06 2.94 r
I_ORCA_TOP/I_SDRAM_IF/U1134/Y (or3c15) 0.28 3.22 f
I_ORCA_TOP/I_SDRAM_IF/U691/Y (clk1b3) 0.13 3.35 r
I_ORCA_TOP/I_SDRAM_IF/U664/Y (or3c3) 0.59 3.94 f
I_ORCA_TOP/I_SDRAM_IF/U1217/Y (inv1a27) 0.11 4.05 r
I_ORCA_TOP/I_SDRAM_IF/U684/Y (or2c9) 0.23 4.28 f
I_ORCA_TOP/I_SDRAM_IF/U1122/Y (or2c15) 0.15 4.42 r
I_ORCA_TOP/I_SDRAM_IF/U670/Y (or2a6) 0.32 4.74 r
I_ORCA_TOP/I_SDRAM_IF/U1114/Y (or2a15) 0.24 4.98 r
I_ORCA_TOP/I_SDRAM_IF/U1226/Y (or2a15) 0.20 5.18 r
I_ORCA_TOP/I_SDRAM_IF/U1111/Y (and2a1) 0.37 5.55 r
I_ORCA_TOP/I_SDRAM_IF/IU504/Y (or2c2) 0.27 5.82 f
I_ORCA_TOP/I_SDRAM_IF/IU546/Y (ao1f2) 0.36 6.18 r
I_ORCA_TOP/I_SDRAM_IF/IU548/Y (oa1f6) 0.11 6.29 f
I_ORCA_TOP/I_SDRAM_IF/U45/Y (and2c2) 0.29 6.58 r
I_ORCA_TOP/I_SDRAM_IF/U30/Y (oa1f6) 0.18 6.76 f
I_ORCA_TOP/I_SDRAM_IF/U1237/Y (and2b3) 0.36 7.12 r
I_ORCA_TOP/I_SDRAM_IF/U1238/Y (xor2b1) 0.26 7.38 r
I_ORCA_TOP/I_SDRAM_IF/U742/Y (ao4e15) 0.41 7.79 r
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[23]/D0 (fdmf2a6)
0.00 7.79 r
data arrival time 7.79
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.58 9.08
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[23]/CLK (fdmf2a6) 9.08 r
library setup time -0.14 8.94
data required time 8.94
------------------------------------------------------------------------------
data required time 8.94
data arrival time -7.79
------------------------------------------------------------------------------
slack (MET) 1.15
Startpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[21]
(falling edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.47 1.47
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/CLK (fdmf2a6) 0.00 1.47 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U195/Q (fdmf2a6) 0.65 2.12 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3891/Y (clk1b3) 0.14 2.26 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U3921/Y (and2a6) 0.23 2.49 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U846/Y (and2a9) 0.23 2.72 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6812/Y (buf1a27) 0.18 2.90 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U251/Y (or2c2) 0.27 3.17 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6241/Y (or2c15) 0.08 3.25 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1702/Y (and3d2) 0.28 3.54 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1682/Y (or3d3) 0.15 3.69 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/data_out_fifo[21] (SDRAM_WFIFO)
0.00 3.69 f
I_ORCA_TOP/I_SDRAM_IF/sd_wfifo_DQ_in[21] (SDRAM_IF) 0.00 3.69 f
I_ORCA_TOP/I_SDRAM_IF/U1308/Y (clk1b2) 0.17 3.85 r
I_ORCA_TOP/I_SDRAM_IF/U1309/Y (inv1a6) 0.06 3.92 f
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[21]/D0 (fdmf1b6) 0.00 3.92 f
data arrival time 3.92
clock SDRAM_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 1.56 5.31
I_ORCA_TOP/I_SDRAM_IF/DQ_out_1_reg[21]/CLK (fdmf1b6) 5.31 f
library setup time -0.23 5.08
data required time 5.08
------------------------------------------------------------------------------
data required time 5.08
data arrival time -3.92
------------------------------------------------------------------------------
slack (MET) 1.16
Startpoint: I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_IF/out_control_reg[26]
(rising edge-triggered flip-flop clocked by SDRAM_CLK)
Path Group: SDRAM_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.61 1.61
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/CLK (fdmf1a3)
0.00 1.61 r
I_ORCA_TOP/I_SDRAM_IF/control_bus_reg[10]/Q (fdmf1a3)
0.65 2.26 r
I_ORCA_TOP/I_SDRAM_IF/U707/Y (clk1b3) 0.22 2.48 f
I_ORCA_TOP/I_SDRAM_IF/U1133/Y (or3a15) 0.40 2.88 f
I_ORCA_TOP/I_SDRAM_IF/U1216/Y (inv1a27) 0.06 2.94 r
I_ORCA_TOP/I_SDRAM_IF/U1134/Y (or3c15) 0.28 3.22 f
I_ORCA_TOP/I_SDRAM_IF/U691/Y (clk1b3) 0.13 3.35 r
I_ORCA_TOP/I_SDRAM_IF/U664/Y (or3c3) 0.59 3.94 f
I_ORCA_TOP/I_SDRAM_IF/U1217/Y (inv1a27) 0.11 4.05 r
I_ORCA_TOP/I_SDRAM_IF/U684/Y (or2c9) 0.23 4.28 f
I_ORCA_TOP/I_SDRAM_IF/U1122/Y (or2c15) 0.15 4.42 r
I_ORCA_TOP/I_SDRAM_IF/U670/Y (or2a6) 0.32 4.74 r
I_ORCA_TOP/I_SDRAM_IF/U1114/Y (or2a15) 0.24 4.98 r
I_ORCA_TOP/I_SDRAM_IF/U1226/Y (or2a15) 0.20 5.18 r
I_ORCA_TOP/I_SDRAM_IF/U1111/Y (and2a1) 0.37 5.55 r
I_ORCA_TOP/I_SDRAM_IF/IU504/Y (or2c2) 0.27 5.82 f
I_ORCA_TOP/I_SDRAM_IF/IU546/Y (ao1f2) 0.36 6.18 r
I_ORCA_TOP/I_SDRAM_IF/IU548/Y (oa1f6) 0.11 6.29 f
I_ORCA_TOP/I_SDRAM_IF/U45/Y (and2c2) 0.29 6.58 r
I_ORCA_TOP/I_SDRAM_IF/U30/Y (oa1f6) 0.18 6.76 f
I_ORCA_TOP/I_SDRAM_IF/U1232/Y (clk1b6) 0.12 6.88 r
I_ORCA_TOP/I_SDRAM_IF/U1233/Y (or2c2) 0.19 7.07 f
I_ORCA_TOP/I_SDRAM_IF/U1234/Y (xor2a2) 0.30 7.36 r
I_ORCA_TOP/I_SDRAM_IF/U744/Y (ao4e9) 0.39 7.75 r
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[26]/D0 (fdmf2a6)
0.00 7.75 r
data arrival time 7.75
clock SDRAM_CLK (rise edge) 7.50 7.50
clock network delay (propagated) 1.59 9.09
I_ORCA_TOP/I_SDRAM_IF/out_control_reg[26]/CLK (fdmf2a6) 9.09 r
library setup time -0.14 8.94
data required time 8.94
------------------------------------------------------------------------------
data required time 8.94
data arrival time -7.75
------------------------------------------------------------------------------
slack (MET) 1.19
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[0] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25560/Y (clk1a15) 0.16 1.16 r
I_ORCA_TOP/CTS_sd_L4I25581/Y (clk1a27) 0.88 2.04 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkm (SDRAM_IF) 0.00 2.04 r
I_ORCA_TOP/I_SDRAM_IF/U1199/Y (mx2a15) 0.51 2.56 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[0] (SDRAM_IF) 0.00 2.56 r
I_ORCA_TOP/sd_DQ_out[0] (ORCA_TOP) 0.00 2.56 r
sdram_DQ_iopad_0/PAD (PDD24DGZ) 2.22 H 4.78 r
sd_DQ[0] (inout) 0.00 + 4.78 r
data arrival time 4.78
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.78
------------------------------------------------------------------------------
slack (MET) 3.11
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[9] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25560/Y (clk1a15) 0.16 1.16 r
I_ORCA_TOP/CTS_sd_L4I25581/Y (clk1a27) 0.88 2.04 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkm (SDRAM_IF) 0.00 2.04 r
I_ORCA_TOP/I_SDRAM_IF/U1168/Y (mx2a15) 0.51 2.56 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[9] (SDRAM_IF) 0.00 2.56 r
I_ORCA_TOP/sd_DQ_out[9] (ORCA_TOP) 0.00 2.56 r
sdram_DQ_iopad_9/PAD (PDD24DGZ) 2.22 H 4.78 r
sd_DQ[9] (inout) 0.00 + 4.78 r
data arrival time 4.78
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.78
------------------------------------------------------------------------------
slack (MET) 3.11
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[29] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25560/Y (clk1a15) 0.16 1.16 r
I_ORCA_TOP/CTS_sd_L4I25581/Y (clk1a27) 0.88 2.04 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkm (SDRAM_IF) 0.00 2.04 r
I_ORCA_TOP/I_SDRAM_IF/U1178/Y (mx2a15) 0.51 2.56 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[29] (SDRAM_IF) 0.00 2.56 r
I_ORCA_TOP/sd_DQ_out[29] (ORCA_TOP) 0.00 2.56 r
sdram_DQ_iopad_29/PAD (PDD24DGZ) 2.22 H 4.78 r
sd_DQ[29] (inout) 0.00 + 4.78 r
data arrival time 4.78
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.78
------------------------------------------------------------------------------
slack (MET) 3.11
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[6] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25559/Y (clk1a15) 0.19 1.19 r
I_ORCA_TOP/CTS_sd_L4I25562/Y (clk1a27) 0.43 1.62 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkk (SDRAM_IF) 0.00 1.62 r
I_ORCA_TOP/I_SDRAM_IF/U1171/Y (mx2a15) 0.39 2.02 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[6] (SDRAM_IF) 0.00 2.02 r
I_ORCA_TOP/sd_DQ_out[6] (ORCA_TOP) 0.00 2.02 r
sdram_DQ_iopad_6/PAD (PDD24DGZ) 2.22 H 4.24 r
sd_DQ[6] (inout) 0.00 + 4.24 r
data arrival time 4.24
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.24
------------------------------------------------------------------------------
slack (MET) 3.66
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[7] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25557/Y (clk1a15) 0.17 1.17 r
I_ORCA_TOP/CTS_sd_L4I25561/Y (clk1a27) 0.42 1.59 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkd (SDRAM_IF) 0.00 1.59 r
I_ORCA_TOP/I_SDRAM_IF/U1170/Y (mx2a15) 0.39 1.99 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[7] (SDRAM_IF) 0.00 1.99 r
I_ORCA_TOP/sd_DQ_out[7] (ORCA_TOP) 0.00 1.99 r
sdram_DQ_iopad_7/PAD (PDD24DGZ) 2.22 H 4.21 r
sd_DQ[7] (inout) 0.00 + 4.21 r
data arrival time 4.21
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.21
------------------------------------------------------------------------------
slack (MET) 3.68
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[23] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25560/Y (clk1a15) 0.16 1.16 r
I_ORCA_TOP/CTS_sd_L4I25564/Y (clk1a27) 0.42 1.58 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clko (SDRAM_IF) 0.00 1.58 r
I_ORCA_TOP/I_SDRAM_IF/U1184/Y (mx2a15) 0.39 1.98 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[23] (SDRAM_IF) 0.00 1.98 r
I_ORCA_TOP/sd_DQ_out[23] (ORCA_TOP) 0.00 1.98 r
sdram_DQ_iopad_23/PAD (PDD24DGZ) 2.22 H 4.20 r
sd_DQ[23] (inout) 0.00 + 4.20 r
data arrival time 4.20
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.20
------------------------------------------------------------------------------
slack (MET) 3.69
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[30] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25560/Y (clk1a15) 0.16 1.16 r
I_ORCA_TOP/CTS_sd_L4I25564/Y (clk1a27) 0.42 1.58 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clko (SDRAM_IF) 0.00 1.58 r
I_ORCA_TOP/I_SDRAM_IF/U1176/Y (mx2a15) 0.39 1.98 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[30] (SDRAM_IF) 0.00 1.98 r
I_ORCA_TOP/sd_DQ_out[30] (ORCA_TOP) 0.00 1.98 r
sdram_DQ_iopad_30/PAD (PDD24DGZ) 2.22 H 4.20 r
sd_DQ[30] (inout) 0.00 + 4.20 r
data arrival time 4.20
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.20
------------------------------------------------------------------------------
slack (MET) 3.69
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[2] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25557/Y (clk1a15) 0.17 1.17 r
I_ORCA_TOP/CTS_sd_L4I25567/Y (clk1a27) 0.41 1.59 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkc (SDRAM_IF) 0.00 1.59 r
I_ORCA_TOP/I_SDRAM_IF/U1177/Y (mx2a15) 0.39 1.97 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[2] (SDRAM_IF) 0.00 1.97 r
I_ORCA_TOP/sd_DQ_out[2] (ORCA_TOP) 0.00 1.97 r
sdram_DQ_iopad_2/PAD (PDD24DGZ) 2.22 H 4.20 r
sd_DQ[2] (inout) 0.00 + 4.20 r
data arrival time 4.20
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.20
------------------------------------------------------------------------------
slack (MET) 3.70
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[8] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25560/Y (clk1a15) 0.16 1.16 r
I_ORCA_TOP/CTS_sd_L4I25565/Y (clk1a27) 0.42 1.58 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkp (SDRAM_IF) 0.00 1.58 r
I_ORCA_TOP/I_SDRAM_IF/U1169/Y (mx2a15) 0.39 1.97 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[8] (SDRAM_IF) 0.00 1.97 r
I_ORCA_TOP/sd_DQ_out[8] (ORCA_TOP) 0.00 1.97 r
sdram_DQ_iopad_8/PAD (PDD24DGZ) 2.22 H 4.19 r
sd_DQ[8] (inout) 0.00 + 4.19 r
data arrival time 4.19
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.19
------------------------------------------------------------------------------
slack (MET) 3.70
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[5] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25557/Y (clk1a15) 0.17 1.17 r
I_ORCA_TOP/CTS_sd_L4I25568/Y (clk1a27) 0.38 1.56 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clke (SDRAM_IF) 0.00 1.56 r
I_ORCA_TOP/I_SDRAM_IF/U1172/Y (mx2a15) 0.38 1.93 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[5] (SDRAM_IF) 0.00 1.93 r
I_ORCA_TOP/sd_DQ_out[5] (ORCA_TOP) 0.00 1.93 r
sdram_DQ_iopad_5/PAD (PDD24DGZ) 2.22 H 4.16 r
sd_DQ[5] (inout) 0.00 + 4.16 r
data arrival time 4.16
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.16
------------------------------------------------------------------------------
slack (MET) 3.74
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[22] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25557/Y (clk1a15) 0.17 1.17 r
I_ORCA_TOP/CTS_sd_L4I25568/Y (clk1a27) 0.38 1.56 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clke (SDRAM_IF) 0.00 1.56 r
I_ORCA_TOP/I_SDRAM_IF/U1185/Y (mx2a15) 0.38 1.93 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[22] (SDRAM_IF) 0.00 1.93 r
I_ORCA_TOP/sd_DQ_out[22] (ORCA_TOP) 0.00 1.93 r
sdram_DQ_iopad_22/PAD (PDD24DGZ) 2.22 H 4.16 r
sd_DQ[22] (inout) 0.00 + 4.16 r
data arrival time 4.16
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.16
------------------------------------------------------------------------------
slack (MET) 3.74
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[31] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25549/Y (clk1a15) 0.14 0.85 r
I_ORCA_TOP/CTS_sd_L2I25554/Y (clk1a15) 0.15 1.00 r
I_ORCA_TOP/CTS_sd_L3I25557/Y (clk1a15) 0.17 1.17 r
I_ORCA_TOP/CTS_sd_L4I25568/Y (clk1a27) 0.38 1.56 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clke (SDRAM_IF) 0.00 1.56 r
I_ORCA_TOP/I_SDRAM_IF/U1175/Y (mx2a15) 0.38 1.93 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[31] (SDRAM_IF) 0.00 1.93 r
I_ORCA_TOP/sd_DQ_out[31] (ORCA_TOP) 0.00 1.93 r
sdram_DQ_iopad_31/PAD (PDD24DGZ) 2.22 H 4.16 r
sd_DQ[31] (inout) 0.00 + 4.16 r
data arrival time 4.16
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.16
------------------------------------------------------------------------------
slack (MET) 3.74
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[3] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25551/Y (clk1a15) 0.12 0.83 r
I_ORCA_TOP/CTS_sd_L2I25555/Y (clk1a15) 0.13 0.96 r
I_ORCA_TOP/CTS_sd_L3I25556/Y (clk1a15) 0.15 1.10 r
I_ORCA_TOP/CTS_sd_L4I25583/Y (clk1a27) 0.43 1.53 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkr (SDRAM_IF) 0.00 1.53 r
I_ORCA_TOP/I_SDRAM_IF/U1174/Y (mx2a15) 0.39 1.92 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[3] (SDRAM_IF) 0.00 1.92 r
I_ORCA_TOP/sd_DQ_out[3] (ORCA_TOP) 0.00 1.92 r
sdram_DQ_iopad_3/PAD (PDD24DGZ) 2.22 H 4.15 r
sd_DQ[3] (inout) 0.00 + 4.15 r
data arrival time 4.15
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.15
------------------------------------------------------------------------------
slack (MET) 3.75
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[13] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25551/Y (clk1a15) 0.12 0.83 r
I_ORCA_TOP/CTS_sd_L2I25555/Y (clk1a15) 0.13 0.96 r
I_ORCA_TOP/CTS_sd_L3I25556/Y (clk1a15) 0.15 1.10 r
I_ORCA_TOP/CTS_sd_L4I25583/Y (clk1a27) 0.43 1.53 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkr (SDRAM_IF) 0.00 1.53 r
I_ORCA_TOP/I_SDRAM_IF/U1195/Y (mx2a15) 0.39 1.92 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[13] (SDRAM_IF) 0.00 1.92 r
I_ORCA_TOP/sd_DQ_out[13] (ORCA_TOP) 0.00 1.92 r
sdram_DQ_iopad_13/PAD (PDD24DGZ) 2.22 H 4.15 r
sd_DQ[13] (inout) 0.00 + 4.15 r
data arrival time 4.15
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.15
------------------------------------------------------------------------------
slack (MET) 3.75
Startpoint: I_CLOCK_GEN/I_PLL_SD/clk
(clock source 'SDRAM_CLK')
Endpoint: sd_DQ[28] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SDRAM_CLK (rise edge) 0.00 0.00
I_CLOCK_GEN/I_PLL_SD/clk (PLL) 0.00 0.00 r
I_CLOCK_GEN/U15/Y (inv1a27) 0.02 0.02 f
I_CLOCK_GEN/U11/Y (mx2d6) 0.13 0.15 r
I_CLOCK_GEN/U20/Y (buf1a27) 0.12 0.27 r
I_CLOCK_GEN/i_sdram_clk (CLOCK_GEN) 0.00 0.27 r
I_CLK_SOURCE_SDRAM_CLK/Y (clk1a27) 0.29 0.56 r
I_ORCA_TOP/sdram_clk (ORCA_TOP) 0.00 0.56 r
I_ORCA_TOP/CTS_sd_L0I25548/Y (clk1a15) 0.14 0.71 r
I_ORCA_TOP/CTS_sd_L1I25551/Y (clk1a15) 0.12 0.83 r
I_ORCA_TOP/CTS_sd_L2I25555/Y (clk1a15) 0.13 0.96 r
I_ORCA_TOP/CTS_sd_L3I25556/Y (clk1a15) 0.15 1.10 r
I_ORCA_TOP/CTS_sd_L4I25583/Y (clk1a27) 0.43 1.53 r
I_ORCA_TOP/I_SDRAM_IF/sdram_clkr (SDRAM_IF) 0.00 1.53 r
I_ORCA_TOP/I_SDRAM_IF/U1179/Y (mx2a15) 0.39 1.92 r
I_ORCA_TOP/I_SDRAM_IF/sd_DQ_out[28] (SDRAM_IF) 0.00 1.92 r
I_ORCA_TOP/sd_DQ_out[28] (ORCA_TOP) 0.00 1.92 r
sdram_DQ_iopad_28/PAD (PDD24DGZ) 2.22 H 4.15 r
sd_DQ[28] (inout) 0.00 + 4.15 r
data arrival time 4.15
clock SD_DDR_CLK (fall edge) 3.75 3.75
clock network delay (propagated) 4.89 8.64
output external delay -0.75 7.89
data required time 7.89
------------------------------------------------------------------------------
data required time 7.89
data arrival time -4.15
------------------------------------------------------------------------------
slack (MET) 3.75
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/TOS_int_reg[0]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/Neg_Flag (CONTROL) 0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/U106/Y (mx2d3) 0.19 4.64 f
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/U104/Y (xor2b2) 0.28 4.93 f
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/U103/Y (and2c6) 0.15 5.08 r
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/U139/Y (mx2d6) 0.21 5.29 f
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/U138/Y (and2c15) 0.32 5.61 r
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/PushEnbl (CONTROL) 0.00 5.61 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/PushEnbl (STACK_TOP)
0.00 5.61 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U119/Y (inv1a9) 0.27 5.88 f
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U1/Y (or2a15) 0.30 6.18 f
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/IU32/Y (or2c15) 0.06 6.24 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U51/Y (xor2b2) 0.33 6.57 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U166/Y (or3d15) 0.10 6.67 f
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U118/Y (and2a3) 0.16 6.83 f
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/U117/Y (and2c3) 0.22 7.05 r
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/TOS_int_reg[0]/D0 (fdmf2a3)
0.00 7.05 r
data arrival time 7.05
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.54 7.54
I_ORCA_TOP/I_RISC_CORE/I_STACK_TOP/TOS_int_reg[0]/CLK (fdmf2a3)
7.54 r
library setup time -0.20 7.34
data required time 7.34
------------------------------------------------------------------------------
data required time 7.34
data arrival time -7.05
------------------------------------------------------------------------------
slack (MET) 0.29
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Oprnd_A_reg[7]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_ALU/Zro_Flag_reg
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Oprnd_A_reg[7]/CLK (fdmf1a9)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Oprnd_A_reg[7]/Q (fdmf1a9)
0.75 3.31 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Oprnd_A[7] (DATA_PATH)
0.00 3.31 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/Oprnd_A[7] (ALU) 0.00 3.31 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/I20/CO1 (facs3a3) 0.33 3.63 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/I21/CO1 (facsf1b3) 0.28 3.92 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/I22/CO1 (facsf2a3) 0.25 4.17 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/I23/CO1 (facsf1b3) 0.24 4.41 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/I24/CO1 (facsf2a3) 0.24 4.65 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/I26/Y (and2c2) 0.09 4.74 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/U705/Y (inv1a1) 0.17 4.91 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/U706/Y (clk1b2) 0.11 5.01 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/U2100/Y (ao1a9) 0.34 5.35 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/I34/S (facsf1b2) 0.36 5.71 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/U654/Y (buf1a27) 0.22 5.93 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/U430/Y (inv1a27) 0.05 5.98 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/U370/Y (and2c15) 0.06 6.04 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/U520/Y (and3d15) 0.19 6.23 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/U319/Y (or2c15) 0.16 6.39 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/U547/Y (and2c15) 0.13 6.52 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/U276/Y (or2c9) 0.11 6.63 f
I_ORCA_TOP/I_RISC_CORE/I_ALU/U332/Y (and3d15) 0.17 6.79 r
I_ORCA_TOP/I_RISC_CORE/I_ALU/Zro_Flag_reg/D0 (fdesf2a9)
0.00 6.79 r
data arrival time 6.79
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.54 7.54
I_ORCA_TOP/I_RISC_CORE/I_ALU/Zro_Flag_reg/CLK (fdesf2a9) 7.54 r
library setup time -0.39 7.15
data required time 7.15
------------------------------------------------------------------------------
data required time 7.15
data arrival time -6.79
------------------------------------------------------------------------------
slack (MET) 0.36
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[2]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U74/Y (oa4f2)
0.30 6.62 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U56/Y (ao1e3)
0.21 6.83 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[2]/D0 (fdesf2a9)
0.00 6.83 f
data arrival time 6.83
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[2]/CLK (fdesf2a9)
7.55 r
library setup time -0.32 7.24
data required time 7.24
------------------------------------------------------------------------------
data required time 7.24
data arrival time -6.83
------------------------------------------------------------------------------
slack (MET) 0.40
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[0]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U76/Y (oa4f2)
0.30 6.62 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U62/Y (ao1e3)
0.22 6.84 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[0]/D0 (fdesf2a6)
0.00 6.84 f
data arrival time 6.84
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.53 7.53
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[0]/CLK (fdesf2a6)
7.53 r
library setup time -0.28 7.25
data required time 7.25
------------------------------------------------------------------------------
data required time 7.25
data arrival time -6.84
------------------------------------------------------------------------------
slack (MET) 0.41
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[1]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U75/Y (oa4f2)
0.30 6.62 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U68/Y (ao1e3)
0.22 6.84 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[1]/D0 (fdesf2a6)
0.00 6.84 f
data arrival time 6.84
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[1]/CLK (fdesf2a6)
7.55 r
library setup time -0.28 7.27
data required time 7.27
------------------------------------------------------------------------------
data required time 7.27
data arrival time -6.84
------------------------------------------------------------------------------
slack (MET) 0.43
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[3]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U73/Y (oa4f2)
0.30 6.62 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U58/Y (ao1e3)
0.22 6.84 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[3]/D0 (fdesf2a6)
0.00 6.84 f
data arrival time 6.84
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[3]/CLK (fdesf2a6)
7.55 r
library setup time -0.28 7.27
data required time 7.27
------------------------------------------------------------------------------
data required time 7.27
data arrival time -6.84
------------------------------------------------------------------------------
slack (MET) 0.43
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[7]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U69/Y (oa4f2)
0.28 6.60 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U55/Y (ao1e3)
0.21 6.81 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[7]/D0 (fdesf2a9)
0.00 6.81 f
data arrival time 6.81
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.58 7.58
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[7]/CLK (fdesf2a9)
7.58 r
library setup time -0.32 7.26
data required time 7.26
------------------------------------------------------------------------------
data required time 7.26
data arrival time -6.81
------------------------------------------------------------------------------
slack (MET) 0.45
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[4]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U72/Y (oa4f2)
0.30 6.62 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U59/Y (ao1e3)
0.22 6.84 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[4]/D0 (fdesf2a6)
0.00 6.84 f
data arrival time 6.84
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.58 7.58
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[4]/CLK (fdesf2a6)
7.58 r
library setup time -0.28 7.30
data required time 7.30
------------------------------------------------------------------------------
data required time 7.30
data arrival time -6.84
------------------------------------------------------------------------------
slack (MET) 0.46
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[5]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U71/Y (oa4f2)
0.30 6.62 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U60/Y (ao1e3)
0.22 6.84 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[5]/D0 (fdesf2a6)
0.00 6.84 f
data arrival time 6.84
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.58 7.58
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[5]/CLK (fdesf2a6)
7.58 r
library setup time -0.28 7.30
data required time 7.30
------------------------------------------------------------------------------
data required time 7.30
data arrival time -6.84
------------------------------------------------------------------------------
slack (MET) 0.46
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[6]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.32 4.77 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.10 4.87 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.05 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.08 5.14 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.17 5.30 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.08 5.38 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.10 5.49 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.31 5.80 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.19 5.99 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U57/Y (or2c3)
0.16 6.15 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U66/Y (clk1b6)
0.17 6.32 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U70/Y (oa4f2)
0.30 6.62 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U61/Y (ao1e3)
0.22 6.84 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[6]/D0 (fdesf2a6)
0.00 6.84 f
data arrival time 6.84
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.58 7.58
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[6]/CLK (fdesf2a6)
7.58 r
library setup time -0.28 7.30
data required time 7.30
------------------------------------------------------------------------------
data required time 7.30
data arrival time -6.84
------------------------------------------------------------------------------
slack (MET) 0.46
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[0]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.39 4.84 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.05 4.90 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.08 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.07 5.15 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.18 5.33 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.07 5.39 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.13 5.53 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.14 5.66 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.17 5.84 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U63/Y (or2c6)
0.28 6.11 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U67/Y (or2a15)
0.35 6.46 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[0]/E (fdesf2a6)
0.00 6.46 f
data arrival time 6.46
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.53 7.53
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[0]/CLK (fdesf2a6)
7.53 r
library setup time -0.59 6.94
data required time 6.94
------------------------------------------------------------------------------
data required time 6.94
data arrival time -6.46
------------------------------------------------------------------------------
slack (MET) 0.47
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[1]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.39 4.84 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.05 4.90 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.08 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.07 5.15 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.18 5.33 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.07 5.39 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.13 5.53 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.14 5.66 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.17 5.84 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U63/Y (or2c6)
0.28 6.11 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U67/Y (or2a15)
0.35 6.46 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[1]/E (fdesf2a6)
0.00 6.46 f
data arrival time 6.46
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[1]/CLK (fdesf2a6)
7.55 r
library setup time -0.59 6.96
data required time 6.96
------------------------------------------------------------------------------
data required time 6.96
data arrival time -6.46
------------------------------------------------------------------------------
slack (MET) 0.50
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[3]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.39 4.84 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.05 4.90 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.08 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.07 5.15 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.18 5.33 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.07 5.39 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.13 5.53 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.14 5.66 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.17 5.84 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U63/Y (or2c6)
0.28 6.11 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U67/Y (or2a15)
0.35 6.46 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[3]/E (fdesf2a6)
0.00 6.46 f
data arrival time 6.46
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[3]/CLK (fdesf2a6)
7.55 r
library setup time -0.59 6.96
data required time 6.96
------------------------------------------------------------------------------
data required time 6.96
data arrival time -6.46
------------------------------------------------------------------------------
slack (MET) 0.50
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[4]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.39 4.84 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.05 4.90 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.08 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.07 5.15 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.18 5.33 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.07 5.39 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.13 5.53 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.14 5.66 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.17 5.84 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U63/Y (or2c6)
0.28 6.11 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U67/Y (or2a15)
0.35 6.46 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[4]/E (fdesf2a6)
0.00 6.46 f
data arrival time 6.46
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.58 7.58
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[4]/CLK (fdesf2a6)
7.58 r
library setup time -0.59 6.99
data required time 6.99
------------------------------------------------------------------------------
data required time 6.99
data arrival time -6.46
------------------------------------------------------------------------------
slack (MET) 0.52
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[5]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Path Group: SYS_2x_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.55 2.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/CLK (fdesf1a6)
0.00 2.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[30]/Q (fdesf1a6)
0.71 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[30] (INSTRN_LAT)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[30] (DATA_PATH)
0.00 3.26 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U121/Y (clk1b3) 0.20 3.46 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U146/Y (or2c15) 0.11 3.57 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U94/Y (and2c9) 0.08 3.65 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U148/Y (or2c15) 0.06 3.71 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U97/Y (clk1b3) 0.13 3.84 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U98/Y (mx2d3) 0.28 4.12 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U149/Y (buf1a9) 0.33 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Neg_Flag (DATA_PATH)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/Neg_Flag (PRGRM_CNT_TOP)
0.00 4.45 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U301/Y (xor2a15)
0.39 4.84 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U331/Y (and2c15)
0.05 4.90 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U47/Y (mx2d6)
0.18 5.08 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U35/Y (or2c15)
0.07 5.15 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U48/Y (mx2d6)
0.18 5.33 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U271/Y (or2c15)
0.07 5.39 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U6/Y (clk1b3)
0.13 5.53 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U10/Y (and2c9)
0.14 5.66 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U65/Y (clk1b3)
0.17 5.84 r
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U63/Y (or2c6)
0.28 6.11 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/U67/Y (or2a15)
0.35 6.46 f
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[5]/E (fdesf2a6)
0.00 6.46 f
data arrival time 6.46
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.58 7.58
I_ORCA_TOP/I_RISC_CORE/I_PRGRM_CNT_TOP/PCint_reg[5]/CLK (fdesf2a6)
7.58 r
library setup time -0.59 6.99
data required time 6.99
------------------------------------------------------------------------------
data required time 6.99
data arrival time -6.46
------------------------------------------------------------------------------
slack (MET) 0.52
Startpoint: I_ORCA_TOP/I_BLENDER/s4_op2_reg[9]
(rising edge-triggered flip-flop clocked by SYS_CLK)
Endpoint: I_ORCA_TOP/I_BLENDER/s5_result_reg[31]
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_CLK (rise edge) 0.00 0.00
clock network delay (propagated) 2.36 2.36
I_ORCA_TOP/I_BLENDER/s4_op2_reg[9]/CLK (fdmf1a3) 0.00 2.36 r
I_ORCA_TOP/I_BLENDER/s4_op2_reg[9]/Q (fdmf1a3) 0.57 2.92 f
I_ORCA_TOP/I_BLENDER/U91/Y (or2c1) 0.39 3.31 r
I_ORCA_TOP/I_BLENDER/U12/Y (ao1f2) 0.29 3.60 f
I_ORCA_TOP/I_BLENDER/U31/Y (oa1f3) 0.30 3.90 r
I_ORCA_TOP/I_BLENDER/IU677/Y (ao1f2) 0.15 4.05 f
I_ORCA_TOP/I_BLENDER/U17/Y (ao1a3) 0.25 4.30 f
I_ORCA_TOP/I_BLENDER/IU726/CO (fa1a1) 0.35 4.65 f
I_ORCA_TOP/I_BLENDER/IU769/CO (fa1a1) 0.38 5.03 f
I_ORCA_TOP/I_BLENDER/IU813/CO (fa1a3) 0.38 5.41 f
I_ORCA_TOP/I_BLENDER/IU852/CO (fa1a3) 0.36 5.77 f
I_ORCA_TOP/I_BLENDER/IU892/CO (fa1a3) 0.36 6.13 f
I_ORCA_TOP/I_BLENDER/IU927/CO (fa1a2) 0.36 6.49 f
I_ORCA_TOP/I_BLENDER/IU963/CO (fa1a3) 0.37 6.86 f
I_ORCA_TOP/I_BLENDER/IU994/CO (fa1a1) 0.36 7.22 f
I_ORCA_TOP/I_BLENDER/IU1026/CO (fa1a2) 0.38 7.60 f
I_ORCA_TOP/I_BLENDER/IU1053/CO (fa1a2) 0.37 7.96 f
I_ORCA_TOP/I_BLENDER/IU1081/CO (fa1a2) 0.37 8.33 f
I_ORCA_TOP/I_BLENDER/IU1104/CO (fa1a2) 0.37 8.71 f
I_ORCA_TOP/I_BLENDER/CU15151_IU1128/CO (fa1a3) 0.37 9.08 f
I_ORCA_TOP/I_BLENDER/CU15170_IU1147/CO (fa1a3) 0.36 9.44 f
I_ORCA_TOP/I_BLENDER/CU15190_IU1167/CO (fa1a3) 0.36 9.80 f
I_ORCA_TOP/I_BLENDER/CU15205_IU1182/CO (fa1a3) 0.36 10.16 f
I_ORCA_TOP/I_BLENDER/CU15221_IU1198/CO (fa1a3) 0.36 10.52 f
I_ORCA_TOP/I_BLENDER/CU15232_IU1209/CO (fa1a3) 0.36 10.89 f
I_ORCA_TOP/I_BLENDER/CU15244_IU1221/CO (fa1a3) 0.33 11.22 f
I_ORCA_TOP/I_BLENDER/U121/Y (xor3a1) 0.26 11.48 f
I_ORCA_TOP/I_BLENDER/s5_result_reg[31]/D0 (fdmf1a3) 0.00 11.48 f
data arrival time 11.48
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.38 12.38
I_ORCA_TOP/I_BLENDER/s5_result_reg[31]/CLK (fdmf1a3) 12.38 r
library setup time -0.31 12.07
data required time 12.07
------------------------------------------------------------------------------
data required time 12.07
data arrival time -11.48
------------------------------------------------------------------------------
slack (MET) 0.59
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1112
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U677/Y (mx2d1) 0.19 11.42 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1112/D0 (fdmf1a6) 0.00 11.42 f
data arrival time 11.42
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1112/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.42
------------------------------------------------------------------------------
slack (MET) 0.63
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1231
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U687/Y (mx2d1) 0.19 11.42 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1231/D0 (fdmf1a6) 0.00 11.42 f
data arrival time 11.42
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1231/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.42
------------------------------------------------------------------------------
slack (MET) 0.63
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1841
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U747/Y (mx2d1) 0.19 11.42 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1841/D0 (fdmf1a6) 0.00 11.42 f
data arrival time 11.42
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1841/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.42
------------------------------------------------------------------------------
slack (MET) 0.63
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2071
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U772/Y (mx2d2) 0.20 11.43 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2071/D0 (fdmf1a6) 0.00 11.43 f
data arrival time 11.43
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2071/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.06
data required time 12.06
------------------------------------------------------------------------------
data required time 12.06
data arrival time -11.43
------------------------------------------------------------------------------
slack (MET) 0.63
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U541
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U628/Y (mx2d1) 0.19 11.42 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U541/D0 (fdmf1a6) 0.00 11.42 f
data arrival time 11.42
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U541/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.42
------------------------------------------------------------------------------
slack (MET) 0.63
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1610
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U5911/Y (mx2d1) 0.19 11.42 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1610/D0 (fdmf1a6) 0.00 11.42 f
data arrival time 11.42
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1610/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.42
------------------------------------------------------------------------------
slack (MET) 0.63
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1721
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U737/Y (mx2d1) 0.19 11.42 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1721/D0 (fdmf1a6) 0.00 11.42 f
data arrival time 11.42
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1721/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.42
------------------------------------------------------------------------------
slack (MET) 0.63
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U961
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U332/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U494/Y (buf1a6) 0.24 10.28 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U331/Y (or2c15) 0.08 10.36 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[8] (REG_FILE)
0.00 10.36 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[8] (RISC_CORE) 0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[24] (SD_W_MUX)
0.00 10.36 f
I_ORCA_TOP/I_SD_W_MUX/U71/Y (ao1e1) 0.23 10.60 f
I_ORCA_TOP/I_SD_W_MUX/U91/Y (inv1a2) 0.17 10.77 r
I_ORCA_TOP/I_SD_W_MUX/U92/Y (clk1b6) 0.06 10.83 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[24] (SD_W_MUX) 0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[24] (SDRAM_WFIFO)
0.00 10.83 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U23/Y (clk1a3) 0.16 10.98 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2081/Y (clk1b6) 0.25 11.23 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U662/Y (mx2d1) 0.19 11.42 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U961/D0 (fdmf1a3) 0.00 11.42 f
data arrival time 11.42
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U961/CLK (fdmf1a3) 12.36 r
library setup time -0.31 12.06
data required time 12.06
------------------------------------------------------------------------------
data required time 12.06
data arrival time -11.42
------------------------------------------------------------------------------
slack (MET) 0.64
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U612
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U195/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U240/Y (or2c3) 0.23 10.27 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U497/Y (inv1a9) 0.20 10.47 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U498/Y (inv1a27) 0.05 10.52 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[11] (REG_FILE)
0.00 10.52 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[11] (RISC_CORE) 0.00 10.52 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[27] (SD_W_MUX)
0.00 10.52 f
I_ORCA_TOP/I_SD_W_MUX/U74/Y (ao1e2) 0.19 10.71 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[27] (SD_W_MUX) 0.00 10.71 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[27] (SDRAM_WFIFO)
0.00 10.71 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U41/Y (clk1a3) 0.20 10.91 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2941/Y (clk1b6) 0.25 11.16 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U636/Y (mx2d2) 0.20 11.36 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U612/D0 (fdmf1a6) 0.00 11.36 f
data arrival time 11.36
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U612/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.36
------------------------------------------------------------------------------
slack (MET) 0.69
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U321
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U195/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U240/Y (or2c3) 0.23 10.27 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U497/Y (inv1a9) 0.20 10.47 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U498/Y (inv1a27) 0.05 10.52 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[11] (REG_FILE)
0.00 10.52 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[11] (RISC_CORE) 0.00 10.52 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[27] (SD_W_MUX)
0.00 10.52 f
I_ORCA_TOP/I_SD_W_MUX/U74/Y (ao1e2) 0.19 10.71 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[27] (SD_W_MUX) 0.00 10.71 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[27] (SDRAM_WFIFO)
0.00 10.71 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U41/Y (clk1a3) 0.20 10.91 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2941/Y (clk1b6) 0.25 11.16 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U6121/Y (mx2d1) 0.19 11.35 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U321/D0 (fdmf1a6) 0.00 11.35 f
data arrival time 11.35
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U321/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.35
------------------------------------------------------------------------------
slack (MET) 0.70
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2761
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U195/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U240/Y (or2c3) 0.23 10.27 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U497/Y (inv1a9) 0.20 10.47 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U498/Y (inv1a27) 0.05 10.52 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[11] (REG_FILE)
0.00 10.52 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[11] (RISC_CORE) 0.00 10.52 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[27] (SD_W_MUX)
0.00 10.52 f
I_ORCA_TOP/I_SD_W_MUX/U74/Y (ao1e2) 0.19 10.71 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[27] (SD_W_MUX) 0.00 10.71 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[27] (SDRAM_WFIFO)
0.00 10.71 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U41/Y (clk1a3) 0.20 10.91 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2941/Y (clk1b6) 0.25 11.16 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U819/Y (mx2d1) 0.19 11.35 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2761/D0 (fdmf1a6) 0.00 11.35 f
data arrival time 11.35
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2761/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.35
------------------------------------------------------------------------------
slack (MET) 0.70
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2931
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U195/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U240/Y (or2c3) 0.23 10.27 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U497/Y (inv1a9) 0.20 10.47 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U498/Y (inv1a27) 0.05 10.52 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[11] (REG_FILE)
0.00 10.52 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[11] (RISC_CORE) 0.00 10.52 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[27] (SD_W_MUX)
0.00 10.52 f
I_ORCA_TOP/I_SD_W_MUX/U74/Y (ao1e2) 0.19 10.71 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[27] (SD_W_MUX) 0.00 10.71 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[27] (SDRAM_WFIFO)
0.00 10.71 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U41/Y (clk1a3) 0.20 10.91 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2941/Y (clk1b6) 0.25 11.16 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U827/Y (mx2d2) 0.20 11.36 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2931/D0 (fdmf1a6) 0.00 11.36 f
data arrival time 11.36
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2931/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.36
------------------------------------------------------------------------------
slack (MET) 0.70
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1421
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U195/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U240/Y (or2c3) 0.23 10.27 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U497/Y (inv1a9) 0.20 10.47 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U498/Y (inv1a27) 0.05 10.52 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[11] (REG_FILE)
0.00 10.52 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[11] (RISC_CORE) 0.00 10.52 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[27] (SD_W_MUX)
0.00 10.52 f
I_ORCA_TOP/I_SD_W_MUX/U74/Y (ao1e2) 0.19 10.71 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[27] (SD_W_MUX) 0.00 10.71 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[27] (SDRAM_WFIFO)
0.00 10.71 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U41/Y (clk1a3) 0.20 10.91 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2941/Y (clk1b6) 0.25 11.16 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U706/Y (mx2d1) 0.19 11.35 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1421/D0 (fdmf1a6) 0.00 11.35 f
data arrival time 11.35
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U1421/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.35
------------------------------------------------------------------------------
slack (MET) 0.70
Startpoint: I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]
(rising edge-triggered flip-flop clocked by SYS_2x_CLK)
Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2161
(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock SYS_2x_CLK (rise edge) 5.00 5.00
clock network delay (propagated) 2.55 7.55
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/CLK (fdesf1a6)
0.00 7.55 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2_reg[24]/Q (fdesf1a6)
0.64 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_INSTRN_LAT/Crnt_Instrn_2[24] (INSTRN_LAT)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Crnt_Instrn[24] (DATA_PATH)
0.00 8.19 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U125/Y (clk1b3) 0.21 8.40 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U151/Y (or3a3) 0.33 8.73 f
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U83/Y (clk1b6) 0.09 8.82 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/U82/Y (mx2a3) 0.32 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Addr_A[1] (DATA_PATH)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/Addr_A[1] (REG_FILE)
0.00 9.15 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U228/Y (clk1b3) 0.19 9.34 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U203/Y (and2a15) 0.27 9.60 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U195/Y (oa4f1) 0.44 10.04 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U240/Y (or2c3) 0.23 10.27 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U497/Y (inv1a9) 0.20 10.47 r
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/U498/Y (inv1a27) 0.05 10.52 f
I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/RegPort_A[11] (REG_FILE)
0.00 10.52 f
I_ORCA_TOP/I_RISC_CORE/RESULT_DATA[11] (RISC_CORE) 0.00 10.52 f
I_ORCA_TOP/I_SD_W_MUX/risc_result_data[27] (SD_W_MUX)
0.00 10.52 f
I_ORCA_TOP/I_SD_W_MUX/U74/Y (ao1e2) 0.19 10.71 f
I_ORCA_TOP/I_SD_W_MUX/sd_wfifo_data[27] (SD_W_MUX) 0.00 10.71 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_data_in[27] (SDRAM_WFIFO)
0.00 10.71 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U41/Y (clk1a3) 0.20 10.91 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2941/Y (clk1b6) 0.25 11.16 r
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U774/Y (mx2d1) 0.19 11.35 f
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2161/D0 (fdmf1a6) 0.00 11.35 f
data arrival time 11.35
clock SYS_CLK (rise edge) 10.00 10.00
clock network delay (propagated) 2.36 12.36
I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U2161/CLK (fdmf1a6) 12.36 r
library setup time -0.31 12.05
data required time 12.05
------------------------------------------------------------------------------
data required time 12.05
data arrival time -11.35
------------------------------------------------------------------------------
slack (MET) 0.70
1
Information: Defining new variable 'pclk_clocks'. (CMD-041)
Information: Defining new variable 'pci_io_ports'. (CMD-041)
Information: Defining new variable 'pci_in_ports'. (CMD-041)
Information: Defining new variable 'pci_out_ports'. (CMD-041)
Information: Defining new variable 'sys_clocks'. (CMD-041)
Information: Defining new variable 'sd_ports'. (CMD-041)
Information: Defining new variable 'sdr_clocks'. (CMD-041)
Information: Defining new variable 'i'. (CMD-041)
Information: Defining new variable 'sd_out_ports'. (CMD-041)
Information: Defining new variable 'all_D0_mux_pins'. (CMD-041)
Information: Defining new variable 'boundary_nets'. (CMD-041)
Information: Defining new variable 'sd_io_ddr_ports'. (CMD-041)
Information: Defining new variable 'all_D1_mux_pins'. (CMD-041)
Information: Defining new variable 'pci_ports'. (CMD-041)
1
pt_shell>
Timing updates: 1 (1 implicit, 0 explicit) (0 incremental, 1 full)
Maximum memory usage for this session: 45.02 MB
CPU usage for this session: 32 seconds
Diagnostics summary: 1 warning, 20 informationals
Thank you for using pt_shell!
Updating preference file: /remote/training/home/anjalika/.synopsys_pt_prefs.tcl